Hi,
I am using USRP X310 with daughterboard TwinRX.
Ineed to stream data via 1Gige or 10GigE ethernet link.
I have found an example code ""USRP RIO Full Ethernet Support.zip 18429 KB"
This project has compiled lvbitx file with it.
if i load this bit file on FPGA, then streaming using its host code is fine.
If i recompile the same FPGA code in this project it gives compilation error as attached.
I have installed labview 2019 and NI-USRP 2019 drivers as mentioned in documentation of this project but still it gives compilation error and these errors are in NI-USRP library VIs "Stream Filter MAC.vi" and "Stream Filter IPv4.vi".
It is strange to see the errors in VIs in library provided by the NI
Please guide me to resolve this issue.
