01-30-2020 11:00 AM
Hello everyone,
I am currently working on some signal processing in the FPGA of the USRP. I started with theUSRP RIO single channel template.
My question might be simple or difficult.
1. I want to generate a simple signal (sine wave), then transmit it through the TX1 port
2. Then, receive it in the input output loop in the FPGA top level code.
3. Then transfer it to a DSP loop via a DMA FIFO, multiply it by 2 and then send it to the HOST
The template does already the first two steps, but the third is the one that I am stuck in.
The problem is that I coudn't change the FIFO that transfers the signal to the Host.
Thank you
03-22-2021 08:45 AM
Hello AliSabra,
is this still an issue? The FIFOs are situated in TX Core.gcdl and in the RX Core.gcdl. You might want to change them there.
Best Markus