Rif.: Standalone running USRP without host PC

[jcho37]

Hi,

I am trying to modify NI USRP (2942, 2952) FPGA code to make it run without host PC.

The application is to use USRP box as RF beaconing device, or sensor device to detect some RF signal patterns and indicate it using AUX output. In any case, I want to use USRP without connecting it to a host PC.

I found one past discussion on this subject and the answer from NI was a recommendation to use an embedded processor version of USRP (2974).  However, this is not the solution I am seeking.  I want to modify FPGA code and initialize the USRP without host control.

I think this is possible because I once saw a people using USRPs without host PC, and transmit/receive data using Ethernet. It was an LTE RRH project. The people were smart but unfortunately, I didn’t talk with them long to ask in detail.

If anyone knows how to make USRP self-run, or knows any useful links, please inform me.

Sincerely,

Thank you

J.   Cho

[cenit85]

That would be extremely useful for me too. Did you do any progress on running USRP without host including the RF part? I was able to run something on the FPGA without any host requirement, but enabling the RF part looks very difficult. Especially setting up the LO, I don't know where to start from

[jcho37]

good to see your posting, cenit85,

we have been trying to solve this and contact NI,
and we have received brief answer from Marcus.

It seems we need to get whole register map information from NI,
but we haven't followed this issue since then.
Hope you or anyone can succeed this and share your knowledge.

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2. I think reproducing the data go over register bus is the only way to achieve standalone. @Zhenyu Gu? , could you please upload the screenshot of the register bus part in the NXG example for customer as a reference. If the customer want to know what data in what format go over the register bus that will be another thing and not the request for the register map.

BTW, I can't find any register map for USRP-2942 (or X310+SBX) whatever from NI or Ettus website.

This is the screenshoot in NXG about configuring register bus in FPGA gvi.

[image1]

[image2]

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as strange as it may sound, there is no way to get a documentation of that register map and command flow. I've tried multiple times and this is just not well written down and it is not supposed to be customer facing as we do have driver VIs taking care of initialization and publishing interdependencies, procedures etc. would just put too much support burden on R&D.

If they really want to go about reverse engineering this themselves, there may be a good starting point in the 802.11 Application Framework where we did exactly that to create a fast attack AGC writing gain settings from the FPGA instead of the Host. We sent gain commands from the host, captured them and then played them back later, whenever we needed to. We have no idea what these commands actually contain so we had to redo this and store the sequence of commands for all desired settings (which were only 3 or 4) and then just call exactly that sequence. The 802.11 Application Framework shows, how to inject those register bus words into the existing architecture.

I'm not sure if that is of any help: LabVIEW (but as far as I know only CurrentGen) has (or will get) an HDL export feature which lets you export your IP into HDL code which then could be embedded on a different platform not supported by LabVIEW FPGA (i.e. the E310 or E320, which are able to run standalone).

BR,
Markus

[jcho37]