Switch USRP RIO front end (sbx, 2952R) between Tx and Rx in FPGA code

[IdarNN]

Hi.

I would like to achieve control of the RF front-ends of the USRP 2952R inside the FPGA code.

I have in the host code seent that all control messages are routed through a fifo (reg.host instruction fifo 0), where they on the FPGA side are decoded and the sent to either the RF0/Control or RF1/Control, or one of the other control buses.

The messages are processed at 40 MHz at the USRP, which I then guess is the register bus speed in the system.

Question 1:

Is it possible to control the following resources from the high speed (200 MHz) FPGA code?:

- The switch between Tx1/Rx1 and Rx2

- TX and RX power enable

- TX and RX mixer enable

My main objective would be to be able to use one antenna for transmit and receive, very quickly switching between the states.

Question 2:

Will the switching be done by control logic on a low-speed bus, even if the register message is sent from the 200MHz code?

Question 3:

Will switching on and off the mixer result in the LO starting at arbitrary phases, or will it remain in a state where coherence can be expected? The main objective of switching off the mixers would be to limit the leak between Tx mixer when in receive state, and vice versa.

Question 4:

In a pdf from Ettus, there is talk about a PLL resynchronization feature in the sbx for use in direction finding, which should have been available around 2012.

https://www.ettus.com/content/files/kb/Selecting_an_RF_Daughterboard.pdf

I cannot find a reference to this anywhere else. Do anyone know about this feature, and how to enable this? Is this something that is done by either "Host driven synchronization.vi" or "FPGA selv synchronization.vi", that can be found under Instrument I/O - Instrument Drivers - USRP RIO - Syncronization ?

[edjones93]

Hello,

I am Ed from National Instruments Applications Engineering. I have been forwarded your query with regards to the USRP functionality with FPGA code.

I have spoken with a colleague regarding your questions to which we believe with question 1, these functions should be possible since you can achieve this when using only the high level functions on the RT. However this is highly dependent on the switch time of the SPDT's which switch the registers so this could potentially be an issue and is better confirmed by implementing the methodology and testing whether this causes issues.

With question 2, we were unsure what you were referring to by low speed bus, could you please clarify further to this effect?

Question 3 we do believe there may be some leakage between the TX and RX from the mixer switching at said rates.

Finally, for PLL clock synchronisation, I believe the following article should be helpful in explaining how this is achieved and how to implement this using the property nodes in figure 5:

http://www.ni.com/tutorial/14705/en/

Best regards,

Ed