how do I set the usrp center frequency in lvfpga

[apchar]

I'm using LVFPGA with a USRP x310. Where are the blocks to control the center frequency of the downconverter ? Sifting through the function library, all I see that relates to the daughterboards is triggering controls. How do I set things like the LO center frequency when doing FPGA side processing ?

[johnr4]

Hello Apchar,

What is the model name of the USRP that you are using?  I'm assuming it is a USRP-294X or 295X device.  Are you using our sample projects or creating a project from scratch?  Our sample projects utilize the IDL which is very helpful when starting the software portion of your system.  In the IDL, the host side code controls the LO frequency.  This information must be passed to the USRP.  I will continue digging into this design, but I encourage you to explore the sample projects if you have not seen them yet.  I will try to locate here FPGA is handling this information.

 Thanks,

[apchar]

Thank you John,

I have an X310 with one CBX-120 RF daughtercard which I understand is almost but not quite identical to a USRP-2943R (120 MHz), the difference being some calibration issues. The example I'm starting with is the only one I've found for FPGA side processing with the X310. It's called BasicTX_BasicRX.lvproj. I think it came with the NI-USRP drivers. Within that project the vi is called Streaming Xcvr (FPGA).vi under the RIO0 (USRP X310; 294xR; 295xR) target.

That's the only example I've found. I'd give up a kidney for a few more.

What is an IDL?

BTW, none of the USRP related blocks have help screens (help is greyed out.) Are they in another download?

Many thanks.

[alynch]

The project that you found is designed to be used with the Basic TX and Basic RX daughterboards.  If you have the latest NI-USRP driver installed, you should have a more up to date sample project accessible from in LabVIEW. Select Create Project from the File menu and there should be a project named NI-USRP Simple Streaming.

There is no way to tune the radio from the FPGA, because all the logic for that configuration is handled on the host. You can change the center frequency within the bandwidth of the daughterboard using the frequency shift DSP.