need a simple example with X310/2943R and lvfpga

[apchar_]

I'm trying to get our USRP X310 (aka USRP-2943R) working with LVFPGA. For FPGA side processing, the only example I've found is the "Streaming Xcvr (FPGA).vi" under the "USRP X310; 294xR;295xR (USRP X310)" target  in BasicTX_BasicRX.lvproj. It is anything but simple, almost entirely undocumented, & I'm having a devil of a time decyphering it. Does anyone have a simpler example of their own for FPGA side processing with the X310 or 2943R? Maybe something from your own explorations or a class. Just something to get started with. Anything.

[muffin.vi]

apchar_,

Have you seen the LabVIEW SDR Community? There might be some examples there that are helpful to you. 

[apchar_]

Thanks muffin but I have been watching that board. All the examples there are for host-side processing.Judging by the one example I have FPGA-side processing is way more complicated. That's why I'm hoping someone has the simplest possible example to give me a place to start.

[Ben_Co]

Hi apchar_,

Unfortunately, between the SDR Community and the Starter Projects, there really aren't more simplistic examples for USRP RIO programming. The starter project code is as complicated as it is because the programming required is complex. I'd recommend looking at some getting started LabVIEW FPGA programming examples to get your feet wet in FPGA programming, and then ask more specific questions regarding the starter projects here on the forums, if you run into trouble or have questions regarding particular functions. 

BeenCoughin

[apchar_]

Thanks Been. I've been through the tutorials for the flexrio. They didnt really prepare me for this.

Sad to hear this is the simplest example. Host side USRP programming is so simple: open, configure, read/write, and close. Just 5 blocks. I was hoping FPGA side processing was as simple or nearly so.

Are you familiar with the BASICTX_BASICRX Streaming_Xcvr (FPGA).vi example? I have so many questions about this thing mostly about the register bus blocks.

Like what do the register bus blocks do ? They are undocumented.

Why does the same register bus block feed what I assume is the same configuration data to 4 different registers?

Why are the register bus blocks fed by the timed loop's fifo. Why keep old setup data around?

 Thanks

[Ben_Co]

Hi apchar_,

The Register Bus and Require Controls/Indicators loop is a loop that was written to set the proper registers on the USRP RIO and set system level settings. This loop is strictly to verify the device gets set up properly to implement the code in the other two loops. This portion is best left alone for the code to work properly. 

What are you trying to achieve through this example? You mentioned processing on the FPGA, are you trying to add particular functionality on the FPGA side of things? Maybe we can help direct you to where you need to add or change code in this example. 

Thanks,

BeenCoughin 

[apchar_]

Thanks Been.

Right now I'm trying to make a simple fpga-side loopback with a fixed delay and frequency offset. If I understand it, this example writes data from the receiver to the host-bound fifo & reads it back from another fifo and sends it to the transmitter. That host & back loop adds a lot of latency. I'm trying to keep everything on the fpga of the x310.

BTW, all the USRP blocks help screens are blank. I've seen this example in a youtube video & saw flashes of help screens during the presentation. I haven't been able to find the original example. The video was dated 2014. 

https://www.youtube.com/watch?v=9R65O5FSSFU

Thank you. I appreciate the help.

Art