Hi guys! I am new to program design using FPGA, and I meet some probelms in experiment. Hope to get some help from you and thank you very much.
I want to design a digital signal processing (DSP) algorithm in FPGA target using myRIO, and in my system the sampling frequency is 10khz. Because of the limited resource of FPGA in myRIO, I use FPGA IP to design digital algorithm which is using fixed-point signal and working with single-cycle Timed Loops. However, the sampling frequency I set for my experiment is 10khz, which is realized in while loops using loop timer. I tried to insert a single-cycle timed loop with 40Mhz into one while loop with 10khz to design the program, but failed.
I am very confuded about the design thougth about my situation. Can you give me some help about digital signal processing (DSP) algorithm using FPGA? Thank you very much.
