Synchronised AI and AO on myRIO Problems

[niNickC]

Hello,

I'm having a couple problems with some FPGA code I'm trying to implement on myRIO.

I have connected the AI to AO on the C connector of the myRIO in order to simply measure back a ramp I am creating:

However, when I read back the voltage ramp I apply, the first value is delayed and inaccruate:



I've uploaded the code, so hopefully you can understand the problem properley.

Thanks for any suggestions!

Nick

[Tom-S]

Hi Nick,

I have replicated your issue and managed to have some success by including some timing in the for loop on your FPGA. I think without any timing in there, the signals are being read before they have been completely output. Give this a try and see you get anywhere with it.

Thanks,

Tom

AE, NIUK

[niNickC]

Hey Tom,

Yea this is the obvious solution and yes putting a big wait between the read a write will 'solve' the problem at the expense of speed which is not desirable.

It also doesn't really answer the problem as it is able to keep up after the 2nd sample so surely it is possible?

Ayway thanks for youe help.

Nick

[Tom-S]

Nick,

So your two arrays will be 1 reading out of sync, just how you have shown in your image - this issue will not be solved by added timing. The issue I managed to solve on my replication was where you had 272 on the reading you were expected to have 200. The first inital high reading is from the last reading of the set array - as you can see, it is essentially just one reading out.

The solution to the out of sync arrays is just to index the arrays with an offset.

I hope this helps,

Tom

[niNickC]

hmm, re-indexing the array is a bit of a 'work-around' and as you have mentioned doesn't solve the anomolous '272'. I really don't want to add any kind of delay in here as I will be implementing some basic control based on the read signals.

Is there anymore information on how the AI/AO nodes are implemented on myRIO?

[Tom-S]

If you look at the specification for the myRIO, you are going to run into a few errors like this if you do not include any timing in that loop.

The FPGA can run at 40Mhz or 25ns sample intervals - and if you include no timing in the for loop it will run at this speed.

The analogue input can run at 500kS/s or 2us sample intervals

& the analgue output can run a 345kS/s or approximately 3us sample intervals.

As you can see there is quite a difference in the timings, and you will be controlled by the largest sample interval, in this case the analogue output.

Tom