myRIO Compile Error

[CarlosOtiniano]

thanks for your reply Sammy_K

[LYu]

hi Mikael,

I'm experiencing the same problem.  Just to clarify, do you create a FIFO as well as a Memory Block?  If so, do you then use the FIFO to transfer data to the FPGA, then write it to the Memory Block?  I'm having trouble finding examples also.  If you wouldn't mind putting a screen shot or similar of your code, I'd really appreciate it!

Thanks,

Lesley

[MikaelHolmstrom]

Yes that is what I'm planning of doing. But not implemented and tested this approach.

[LYu]

Would you mind posting anything if you get it to work?  I'm trying to put together a simple example now but am stuck in getting data down to the FPGA using FIFO.  I've had trouble finding an example as well.

Thanks!

[jorgeinSD]

Hello,

Same problem here; the bug is that we're allowed to create the FPGA Write Memory block node in an RT VI, leading us to believe it's possible. I finally read the LabVIEW Help for the Write Memory method which states in the Data Parameter description that it "cannot directly write to the data in the memory of the FPGA target from the host VI."

The workaround is to use a DMA FIFO to transfer data to FPGA and move to FPGA RAM for playback.

I hope this helps !

Jorge