Hi Tom,
Thanks a lot for your help.
However I am still running in some problems. I made two loops to see what is going on. One single cycle loop and one while loop as you suggested.
I added two clip module to the FPGA which i called test1 and test2. The attachment shows my vi.
Hoewever, when i run the code and measuring the outputs with an oscilloscope, only DIO7 seems to give an output, which is 20MHz. DIO0 seems to output a logic 1, DIO1 seems to output 0 and DIO6 seems to output 0 as well. Any idea why this happens? Any tips on how to get the full speed (40 MHz) clock output to work?
As attachments i added the VI and the expected behavior.
The vhdl code:
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity test is
Port (
clock : in STD_LOGIC;
reset : in STD_LOGIC;
d0 : out STD_LOGIC;
d1 : out STD_logic
);
end test;
architecture Behavioral of test is
signal l1,l2 : std_logic;
begin
d1 <= clock;
test_proc : process (clock)
begin
if rising_edge(clock) then
if reset = '1' then
l1 <='0';
else
l1<= l1 xor '1';
d0 <= l1;
end if;
end if;
end process;
end Behavioral;
