simple question about simple code for myRio

[Anton.S]

Hi!

Today I started to play with myRio hardware.
I did simple code (snippet is attached).
I thought that this code was transfered to this circuit (picture is attached too). With 40 Mhz reference clock.
But measurements by oscilloscope demonstrated that it is not true. Period was 200ns instead of 50 ns.
What is the real implementation of such piece of code ?

thanks!

[Anton.S]

I found some explanation in help "Using Single-Cycle Timed Loops to Optimize FPGA VIs (FPGA Module)"

http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpgaconcepts/using_sctl_optimize_fpga/ 

It seems like I can have additional FF inside loop (code1.png) and clock enable (actually disable) signal for 2 clock cycles before loop iteration.

Is my suggestion right one?

[alcava.cr]

Hi IIvan, This help topic (Dataflow and the Enable Chain in FPGA VIs) should illustrate what is happening on the background. As you can see there are some additional flip flops added to ensure the dataflow. This translates in extra clock cycles required to execute.

Indeed, the single-cycle Timed Loop (SCTL) is the way to ensure the code will execute in a single tick because it prevents the addition of the enable chain to the code but, take in consideration the limits or the digital ports.

According to the manual, since the Minimum pulse width of myRIO is 20 ns using a 40 MHz clock (= 25 nSec) is within the specifications. I just wanted to point this out in case you would like to go faster using a derived clock.

I hope this helps

[Anton.S]

Hi!

Thank you! In general I understood that "Timed Loop" executed for 1 clk cycle and "Loop" can executes many clk cycles.
I got 50 ns period for my snipped code with Timed Loop.

But how many additional register's I will get with Loop ? How to optimize it ?

For example, I added Z-1 delay in my code. In other systems (previously I used Matlab with Xilinx System Generator Tool) it represented just as additional flip-flop.
With "Timed Loop" and Z-1 added I got 100 ns period as expected (50ns loop cycle + 50ns z-1 delay).
With "Loop" and Z-1 added I got 400 ns! It looks like Z-1 mean not additional trigger, but additional whole loop cycle time (200ns + 200ns).

Am I right ?

[Anton.S]

Scope pictures for previous post.

I know that this is low level things and many users don't care about it.

But in my case we plan to build time critical system (in future it will be based on NI7856R) and data latency is very important for us.

[alcava.cr]

How many additional register's? …as mentioned on the help topic: “each function or VI takes a minimum of one clock cycle”. This means that you will get at least one additional flip flop per fundamental VI, function, conditional terminal, indicators. Regular loops have to iterate and check for a stop condition so that means 2 ticks.

How to optimize it ? …you already found the answer in the SCTL. I recommend checking the link above, is an FAQ that can give you more details.

If you read in detail this information you will also find that there are some exceptions such as analog input operations, which can take hundreds of clock cycles, depending upon the complexity of the operation and hardware limitations.

Again, here is another good help topic that can help you understand more about latency (Understanding Timing Considerations for FPGA VIs).

[Anton.S]

Thank you for the explanation.
May I ask particular question ?
How to program such task:

I have two functions which requires many clock cycles to calculate (math or AI/AO).
For example f1(x) is math1(or AI) and needs 100 clk to execute. And g(f(x))) is math2 (or AO) and needs 150 clk to execute.
Second function is dependent of first function output.
How to write code for parallel execution of both functions with only 1 register to store results ? because latency of calculation is important.

In HDL language it is simple task. I should have start syncronizing tick (CE) then wait time of longest function and save output to register.

My english isn't good, so I painted my task.

[alcava.cr]

Hi IIvan,

Take a look at the following articles for ideas to implement your code:

1. Creating Triggers and Counters

2. Pipelining to Optimize FPGA VIs

3. Transferring Data Among Parallel Loops

I hope this gets you on the right direction.

Regards,