Cannot synchronize counters on PCI-6602

[AtomicDino]

My experimental situation employs pulsed laser micromachining. The laser is externally trriggered with TTL pulses, but sometimes pulses are not triggered because the external TTL trigger is not synchronized to the laser controller's internal clock signal. The missing pulses can be observed by focusing into a sensitive photoresist translated on a nanopositioning stage such that individual pulses are well-separated, and gaps between holes are readily apparent when pulses are skipped. Using internal triggering of the laser there are no gaps, so it is not a problem with the laser itself.

For my application I need to synchronize the fast (38 MHz) reference TTL signal from the laser and the external TTL trigger at a user-defined frequency from 0-250 kHz. The user-defined TTL signal is generated by the nanopostioning stage controller, which does not have an input for the TTL reference signal from the laser, so the signal synchronization must be handled separately.

I have already thoroughly searched the posts on the forum and example VIs for solutions and tried numerous approaches pursuant to those posts, but I cannot get the signals synchronized. I am running the most current LabVIEW 15 SP1 f1 and DAQmx 15.5 with a PCI-6602 as in the attached block diagram image, with an SB-68 connector block. RegA is the laser reference signal at 38 MHz (CTR1 GATE on PFI34), A3200 is the nanopositioning stage controller signal (0-250 kHz) generated only when machining and idle otherwise (CTR2 GATE on PFI30), and Pulse Out is the TTL signal output to be synchronized with the RegA clock (CTR0 OUT on PFI36). I have verified with the test panels in NI MAX that both counter inputs work on the correct PFI lines, and the retriggerable output also behaves properly. My test case is using a 10 kHz generated signal (50 microseconds low, 50 microseconds high, 50% duty cycle), but the actual working version will input the same user-defined frequency as the A3200.

I first constructed this synchronization VI several months ago. In that early version I wired the 80 MHZ timebase into the RegA's counter terminal instead of PFI9, and ran one photoresist test that had no gaps. Thinking that I had a working solution, I perhaps naively stopped there without conducting further tests. Since that time I have patched LabVIEW (f1) and updated DAQmx from 15.0 to 15.5, and tried to replace the PCI-6602 with a new PCIe-6320. However, the 6320 yields the same result.

From what I have read, using the RegA signal as the sample clock should allow the PCI-6602 output signal to synchronize to it. However, tests with the photoresist always show gaps, and it does not appear that having the RegA signal even connected makes any difference. I am at a loss as to why the synchronization is not working and would appreciate any advice.

[Kevin_Price]

Lots of good info there, but I'm still not clear on the following:

*Exactly* what do you mean by synchronization?  What timing relationships need to be controlled and exactly how?

My best guess is that the snippet below may get you closer.   Here the 38 MHz external clock (PFI34) is used as the timebase for pulse generation

and the variable freq signal (PFI30) is used for re-triggering.  I don't think you need the edge-counting tasks at all.

Note however that 38 MHz is pretty fast for an external timebase clock signal.   If I recall correctly, the 6602 is spec'ed to handle faster external clocks than most multifunction boards, such as your X-series.

-Kevin P

[AtomicDino]

Kevin,

Thanks for your speedy reply. I wanted to try your suggestion, but our cooling system shut down this afternoon and the laser will not be operational for a couple of days. However, I was able to look at the output of the VI on an oscilloscope and found that I had to make the High Ticks value half that of the Low Ticks to achieve a 50% duty cycle pulse train. Puzzling....

Regarding your question of what specifically needs synchronization, the laser is actually a regenerative amplifier (hence, 'RegA') seeded by a Tsunami Ti: Sapphire femtosecond laser running at 76 MHz. A fast photodiode in the Tsunami measures this rate ('Sync Out') and is connected to the RegA controller as the Photodiode Input signal. The controller has a Photodiode Reference Out signal based on this Photodiode Input (also at 76 MHz), which we have connected to an oscilloscope for diagnostics, and also outputs an amplified TTL version at 38 MHz, which is the Reference signal I am accessing on PFI34. Pulse ejection is controlled by a Pockels cell in the RegA cavity.

The external TTL signal used to trigger the RegA (Pulse Out in my diagram) has to be phase-locked with the 76 MHz Photodiode Reference Out signal from the seeding source (Tsunami) or, equivalently, the 38 MHz TTL Out signal, in order to eject pulses from the cavity at the correct time. Without the phase-locked trigger, pulses can be ejected before they have made sufficient round trips (~21) in the cavity to build up energy.

Perhaps overly detailed, but I hope that clarifies the situation.

[luda.mattski]

I think Kevin is definitely on the right track with his suggested snippet.  The rest of this post likely won't resolve the issue, but it should provide some insight about synchronization architecure. 

Right now, it looks like you have two master tasks (the two tasks that start at the same frame in the flat sequence structure).  If you want one of them to be a true master task which dictates execution of the other slave tasks, throw the two slave tasks in the first frame of the sequence structure to start them before the master task.  

Regarding hardware-timing your system, with counter inputs and outputs you will probably want to use "implicit" timing, which basically creates its own sample clock based upon the counter source being generated.  Referencing a sample clock for counter operations just doesn't make much sense.  

[Alexander_Sobolev]

I am VERY suspicious about generating pockels cells triggers based on 6602. As far as I know, you need to adjust position of the pockels cell trigger between 38 MHz pulses with sub ns resolution, 6602 can shift only with 1/38M = 25 ns steps. If 6602 phase locks with 38M signal, you can try to adjust delays using cables of variable lengths, but no. 

If you trigger SDG (Amplifier controller) that is phase locked to 76 MHz and controls _both_ pockels cells, external trigger does not need to be synced to seed (at least with the ones we worked). Is this requirement in its specifications?