Synchronizing counter output write to digital output

[dankaroll]

Hi all,

I have a question regarding writing to the counter outputs on a cDAQ-9188 with a NI 9401 module and synchronizing them with a digital output on a NI 9403 module.

Currently I am accessing the four on-board counters of the 9188 through the 9401 module, which are being used to create a 5kHz pulse train with a variable duty cycle to control four independent voltage outputs through a PWM chip. Whenever my main program is executing, I have a sub vi looping in the background which reads the requested values of the 4 channels through a functional global and calculates the corresponding on and off times. Within the same loop, I'm also building a boolean array which controls the enabling of the voltage output, its polarity and a reference digital output if the requested voltage in the current loop iteration was different than the last iteration (value changed indication for an analog trigger). After all of these values are determined, the counter writes to all four counter outputs and the digital output array is written.

Ideally, I would like "the value changed indication" to line up exactly with the counter write, but doing a millisecond timer outside my digital and counter writes showed the counter write took 20 ms to execute and the digital write took 2 ms to execute.  Is there any way to synchronize these two writes to they occur at the exact same time?

Thank you,

[JustJohn]

Hi dankaroll!

The problem you described seems relatively complex and it might be helpful to have a screenshot of your code to see what is actually happening. As far as synchronization is concerned, it seems like it is possible to synchronize the two tasks. Is the issue related to the fact that one task takes 20ms and the other takes 2ms? If this is the case you could potentially start them simultaneously, but they still might not end at the same time. Does the digital write have to wait for the counter write to execute before it can start? Or are they independent?

Just to be clear, your system has 4 counters that create 4 separate 5kHz pulse trains with variable duty cycles that then control the 4 separate voltage outputs of the PWM chip. There subVI is polling for the requested duty cycle for these counters and changing their high and low times accordingly. Inside of this loop that is polling for the proper data for the counter outputs, there is also a boolean array that controls 3 different things. First being if the voltage outputs are on or off coming from the PWM chip, second being the polarity of the voltage output, third being a reference digital output that changes depending on if the current value (duty cycle?) requested is the same as the last iteration.

Clarifying these things will be very helpful and get us pointed in the right direction!

I hope you are doing well!

[dankaroll]

Hi JustJohn

Thank you very much for taking the time to reply to my question. I will try to answer everything as clearly as possible. 

Yes, the system has 4 counters that create 4 separate 5kHZ pulse trains which supply 4 PWM chips to create a voltage output. The duty cycle of these on and off time's need to be adjustable on the fly as each one is controlling the voltage output to a standalone test station. These requested voltage outputs are checked within a polling subvi, where new counter values and a corresponding boolean array are written on each iteration.

It seems you have an understanding of the boolean array but let me give a little more clarification. Each voltage output has two "digital modifiers". The first digital modifier is if the output for that line is enabled or disabled (ON is LOW), and the second is the polarity of that output signal (POSITIVE is HIGH). Each iteration these modifiers are analyzed, and a boolean array is created in the following format [EN1,EN2,EN3,EN4,DIR1,DIR2,DIR3,DIR4,VD1_2,VD3_4].

VD1_2 and VD3_4 are boolean outputs that are turned on if the requested voltages from lines 1 and 2 or 3 and 4 are different from the last iteration. One of the tests done to a part on the test station is a time critical test where I need to measure the reaction time of the part to a change in voltage, so I use VD1_2 or VD3_4 to trigger an analog read in a seperate test program. 

The issue here is that the counter values are being updated far slower than the digital values, so although my trigger has went active the actual voltage to the part under test has not changed. Ideally I would like the digital write to occur exactly on the first rising edge of an updated counter. I have attached a screenshot of the controlling VI. I did not include any timing vi's as I could not get them to work properly. Apologies for the messy coding.

Also, here are some scope traces to show what's actually happening.

Blue- The voltage output at the actual part under test

Green - The counter ouput directly off the NI 9401

Purple - The EN3 digital signal

Yellow- The VC3_4 digital signal

Turning on the part under test: 

Turning off the part under test:

[JustJohn]

Hi dankaroll!

One thing you could try is to have both the counter and the digital output use the same reference timer. This would get them operating on the same clock and potentially solve the issue of them not being synchronized. This would require them to both have timing configured and be referencing the same clock. The point you highlight in the beginning of the code with "Add timing Here" would be a good spot for a timing configuration VI and you specifiy the same clock for both the digital out and counter out. This means you also need to change the timing vi of the counter out task and change them both to sample clock and specificfy the same source. 

[dankaroll]

Hi JustJohn

Maybe you can clear up a couple issues I'm running into with setting the timing. 

I've changed both to run off of a sample clock with the 20MHzTimebase as the source. It is worth noting that the counter cannot run of the OnboardClock on a cDAQ. It is also worth noting that you cannot have multiple timers in the same task if you would like to use a sample clock, so I've reduced my VI down to only run 1 channel for the sake of testing.

When I try to start my digital task in either "Finite Samples" or "Continuous Samples" mode, I generate the following error:

Generation cannot be started because the output buffer is empty.  

Ok, but I don't really want to buffer data, I just want to write it once at every loop iteration.

[JustJohn]

There is a third option using Hardware Timed Single Point. This should do what you are describing in your post. Is this option not available for you in this VI? It might require a bit of code changing to accommodate the non buffered acquisition, but it will get one piece of data per iteration which is what i believe you are looking for.