Counter problem

[Fraçois4]

I’m using the PCI-MIO-16E-4 board with the BNC-2110. I made a setup that is latching the Gi_HW_Save_Register on both rising and falling edges of the G_GATE signal. The G_GATE source that I use is the PFI2 input. The setup works pretty well except that once in a while the Gi_HW_Save_Register doesn’t latch on an edge, whether it’s rising or falling. I know that the board receives the edge because I also use the Gi_Gate_St bit. The frequency used on the G_GATE signal is 10kHz. What can be the problem?

[gus]

Offhand, the only thing I could think is that a gate signal is missed. Does Gi_Gate_Error_St go true when you miss counts?

gus....

[Fraçois4]

The Gi_Gate_Error_St doesn't go true each time I miss counts. Is it possible that the Gi_HW_Save_Register doesn't latch if I'm reading it at the exact same time that it's trying to latch a new value?

[gus]

Two more questions:
Can you post your code? That might provide some insight.
Does the Gi_Gate_Error state ever go true?

I also don't quite follow how you are using the Gi_Gate_St bit. Can you explain that a little more?

gus....

[Fraçois4]

Hi Gus,

The Gi_Gate_Error_St does go true at the end of each period of the gate signal. That signal is a squarewave with a 1ms period and a 50% pulse width.

I'm using the Gi_Gate_St bit because I need to know the state of the gate and the moment when the state changes. I'm only reading the Gi_Gate_St bit.

I'm sending you the part of my code where I'm reading the G0_HW_Save_Registers, the Gi_Gate_St and the Gi_Gate_Error_St. The code is in C language.

Code:
/******************************************************************************************
val.reg.low_reg = DAQ_STC_Windowed_Mode_Read(base, G0_HW_Save_Registers_Low);
if (val.reg.low_reg < old_low_reg) {
val.reg.high_reg = DAQ_STC_Windowed_Mode_Read(base, G0_HW_Save_Registers_High);
} old_low_reg = val.reg.low_reg;
y[1] = (real_T) val.val;
y[2] = (DAQ_STC_Windowed_Mode_Read(base, G_Status_Register) & 0x4000)/16384;
if(y[2]>0){
STCWRITE16 DAQ_STC_Windowed_Mode_Write(base, Interrupt_A_Ack_Register, 0xC060);
}
y[0] = (DAQ_STC_Windowed_Mode_Read(base, Joint_Status_1_Register) & 0x0004)/4;
******************************************************************************************/

Description:
-base is the base address of the PCI-MIO-16E-4 board
-I'm using a union to get the two parts of the G0_HW_Save_Registers.
That union is define this way:
/****************************************
typedef union counter_tag {
struct reg_tag {
unsigned short low_reg;
unsigned short high_reg;
} reg;
unsigned int val;
} counter_val;
counter_val val;
****************************************/
-I'm reading the high part of the G0_HW_Save_Registers only when the low part roll over.
-I'm using the y[0] output to plot the Gi_Gate_St bit, the y[1] output to plot the G0_HW_Save_Registers and the y[2]output to plot the Gi_Gate_Error_St bit.
-I'm also reseting the Gi_Gate_Error_St bit when it comes true with the Gi_Gate_Error_Confirm bit.

Thanks

François Perreault

[gus]

If the Gi_Gate_Error_St goes true at all, then you are having a problem. Can you post the setup code for this app? I'm not exactly sure what you're doing in this app, but it appears that you're writing an optimized event counting application? Can you give more info on what your desired outputs are?

[Fraçois4]

I solved the problem. I was trying to read the Gi_HW_Save_Register at the exact same time that it was trying to latch a new value. The Gi_Gate_Error_St was going true because of that reason.

Thanks for helping me.

François Perreault