Impact of high, derived clock rate

[sbailey64]

I am contemplating the use of the Compact RIO system for a laser instrument that requires high speed gating. I understand the FPGA portion of Compact RIO runs at a default rate of 40 Mhz, but the user can derive slower or faster rates...upwards of 200 Mhz. My questions then are:

1. With a 200 Mhz derived rate, I could write or create a Single Cycle Timed Loop to implement a Counter with 5 ns resolution...correct?

2. With this new, faster derived rate...I am assuming existing I/O functions may not work as originally designed. Would a solution be to create additional Single Cycle Timed Loops to connect these I/O functions to say the RT system where the cycle time (or ticks) are some multiple of the now 200 Mhz derived rate. In other words, if a tick is now 5 ns...have this loop wait 200 ticks (1 us) before running again...giving the I/O 1 us to complete before the next cycle. 

Thanks,

Steve

[Pcorcs]

Hello Steve,

When defining the timing parameters for a Single Cycle Timed Loop (SCTL), each SCTL may be associated with a derived clock of your choice, while maintaining a 40 MHz top level execution rate. 

I am not clear on your intention in section 2. Could you please clarify the purpose of the additional SCTLs? 

Though this acceleration to 200 MHz is possible, the module operation at this loop rate may not be a supported task for the hardware, as the I/O topology was designed for the 40 MHz execution rate. For this type of application, RT PXI with a Flex RIO device may better fit the performance specifications, and would offer the option of developing customized front end circuitry better suited to the application. Please see the link below for additional information:

NI FlexRIO

http://www.ni.com/flexrio/

Please post any additional questions.

Cheers!

[sbailey64]

Hi PCorcs,

In reference to #2, here is what I would like to do. I would like to create a gated counter (in FGPA space) with a 200 Mhz clock. Can I still somehow make other C modules work with the FPGA backplane if my derived clock is now 200 Mhz?

Thanks again,

Steve

[Pcorcs]

Hello Steve,

Derived clocks on the FPGA are different from the Top Level Timing Source. By default, LabVIEW FPGA applications maintain a 40 MHz top level timing sequence, while Single Cycle Timed Loop have a selectable timing source. When using SCTLs, you may elect to use either a derived clock or the Top Level Source. Multiple loops can execute simultaneously at different rates, based on your selected clock configuration. Please see the video demonstrations linked below for a more detailed explanation of this operation:

(Note: Microphone volume is very quiet, you will need to increase your system volume significantly to hear the narration.)

Configure FPGA Clocks Part 1

http://www.screencast.com/users/Patrick_Corcoran/folders/Jing/media/374e6b30-45a4-4028-b2de-4d113e6d...

Configure FPGA Clocks Part 2

http://www.screencast.com/users/Patrick_Corcoran/folders/Jing/media/b843d308-0c43-4e97-a9b4-7ecd4211...

Please post any additional questions, or comments on these videos. 

Thanks!

[sbailey64]

Hi Pcorcs,

I think I understand now and have refined what I'd like to do. I'd like to create a SCTL with a 200 Mhz derived clock. All I want this SCTL to do is create a gate pulse based on an input trigger. As long as I do all my regular I/O in a regular while loop (running at the base rate of 40 Mhz)...I should be OK??

Thanks,

Steve

[Pcorcs]

Steve,

From a software standpoint, yes you should be Ok. The concern in this application would be the digital input topology of the C-Series module. The module is supported at the 40 MHz level, but accelerating to a 200 MHz derivied clock may adversly affect signal integrity. I reccomended the Flex RIO option, mainly because the hardware input topology is designed to accept digital input at this rate. You will need to implement a test with a digital C-Series module to verify that the signal is acquired as expected. 

Best,

[sbailey64]

Hi PCorcs,

We really have a compelling reason to go with the C-modules. Here is the complete scenario. Our input trigger is running at 300 khz. This will enter our system via a C-module I/O card (NI 9402). This trigger will then drive the 200 Mhz, SCTL gate-pulse. This pulse will then gate a counter. It is not clear (yet) if this counter is in FPGA space or C-module space. In any event, does this sound more reasonable?

Thanks,

Steve

[Pcorcs]

Hi Steve,

The counter will be defined in software, and uploaded to the FPGA chip. The problem lies in transmitting a 200 MHz signal from the FPGA, through the C-Series Module, and out to your laser. My concern is that the gated digital waveform will not be resolved correctly at 200 MHz after passing through the C-Series I/O circuitry. I am currently setting up a test system with a 9402 C-Series module. I will post the output waveform, when it is acquired. Perhaps, looking at the output you will be able to make a determination if it will be an acceptable gating signal for the instrumentation.

Cheers!

[sbailey64]

Hi PCorcs,

I may have been unclear on my scenario. We will not be driving a laser with a gated-pulse. The laser (300 khz signal) will be driving a gated-counter (200 Mhz bandwidth). In other words,, the 300 khz laser pulse will be input to a 9402.

Thanks,

Steve

[Pcorcs]

Hello Steve,

Sorry for my delayed response. Thank you for clarifying the application setup. The 300kHz input scenario is certainly a feasible I/O application for the digital C-Series modules. Is the intent of this application to measure the Laser On//OFF Time within 200 MHz?

I believe the hardware setup will meet the requirements you have outlined, as the counter will be controlled entirely in the FPGA space. We have also successfully compiled a simplified counter application with digital I/O inside a 200 MHz SCTL.

Thank you for your posts. Please post back any further questions you may have.

Thanks,