NI 9361 Pulse Width (FIFO Overflow)

[Chnkv]

Hello Everyone!

So I am trying to to measure Duty cycle of an incoming pulse train! I do that in LabView FPGA module (cRIO 9045) and the indicators on the front panel seem to indicate that the code is fine. However, I want to transfer each measurement to the real-time VI and display it on a graph. The problem I am running into is that the FIFO on the FPGA end overflows almost instantly when I run the code. I was able to get the code to display another set of measurement (from an ADC) on the real-time VI (transferred from the FPGA VI), but I cannot get this particular measurement to work. I have tried increasing the buffer size but it still overflows. Below is a picture of the code!