1. This is a physical limitation of the pulse generation hardware. The minimum allowed low time and high time for a pulse train will be 2 edges of the timebase clock. True 0 is not possible. (There is a similar maximum equal to the largest 32-bit unsigned int).
2. Many external devices won't show any difference in behavior between 100% duty cycle and 99.98% duty cycle. In these cases, you just accept the limitation and keep your data acq tasks and software fairly simple.
3. Another idea might work to give true constant-high or constant-low, but I'm not near hardware to be able to test & verify. The concept goes like this:
a. Configure your PWM output to be pause-triggered by a static digital output bit.
b. In software, you'll normally set that bit to mean ON before starting the PWM task.
c. When you want a true 0 or 100% duty cycle, you'd first change the pulse properties on the fly so that your desired state is the Max allowed value and the other state is the Min. The output will very soon be going to the state you desire and staying there for a considerable duration. Your job is to wait just long enough for it to get to the desired output state, then turn the pause-triggering digital output bit to OFF before it leaves that state.
d. Hope that pause-triggering is implemented on the input side. If so, then setting the pause-triggering bit OFF prevents the pulse generation from reacting to timebase clock edges. Thus it remains stuck at the desired output state as long as you wish. If it's implemented on the output side, the PWM output might always revert to idle state when the pause trigger is OFF. Then you could generate a true 0 but not a true 100. I would think it's more natural and sensible to implement on the input side though.
-Kevin P.
*** edited for clarity ***
Message Edited by Kevin Price on 12-14-2006 10:52 AM
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