PCI26251 counter operation

[Agent K]

Hi

I am using NI's PCIe6251 hardware. I have set up the card's2 counters  to clock in data(shift register) and provide waveform triggers for an ADC .  Note, the 2 counters are going to separate pins on the chip.  Unfortnately, when I pulse CTR0 it cause a CTR1 to pull high for the same duration. The figure below shows this effect capture on an scope.

 

However, the converse it not true.  Both CTR0 and CTR1 share essentially identical Labview Code.  They opearate in run-stop sequuence (Ctr0 run, Ctr0 stop, Ctr1 run, Ctr0 stop) for fixed numer of cycle on the main VI at a higher level.  I am at a loss to explain this. If any has run to this or know what is going on here, I would greatly appreciate it. 

Thanks

Neil

[Ryan_T]

Hi Agent K,

After taking a look at the code that you posted along with the description of the issue I see how you are generating the waveform, but could you fill me in on how you are generating the actual pulse.  I may be missing something, but I do not see any harware configuration.

Thanks

[Agent K]

Hi Ryan,

Sorry, there was a reason I append the file name with "write."   Please see the VI.

Thank you,

Agent K.

[Ryan_T]

Hi Agent K,

Unfortunately I am missing some of the VIs in your code, is the ShiftRegisterV01.vi a subVI that you created?  Do you have another card that is similar or has two counters so that we can try the code with it as well to see if this is something related to that specific card or something with the code?

[Agent K]

Ryan,

Unfortunately I do not have another NI cards.  However, I have attached the VI and its complete subVI in the zip.  Hopefully you can view the code completley.

Thanks,

Neil

[stilly32]

Hi Neil,

I can see where this is confusing - you are running into two behaviors that are not at first apparent. First, when you generate a finite pule train with M Series, you actually use both counters, one to generate the pulse train, and one to generate a gating signal (there is a good diagram in the user manual). You're seeing both on the scope because you're running into is a counter behavior called "lazy uncommit" where basically once you or DAQmx route a counter output to a specific terminal, it stays there. You can fix this by tristating the output terminal. This is briefly mentioned in "Counter Parts in NI-DAQmx" in the DAQmx help.

So when you generate on counter 0, it keeps counter 0's output on that PFI line. When you generate on counter 1, counter 0 generates the gating pulse which shows up on the output since it still is routed. To fix this, you can either reset the board in between each generation, or tristate the output terminal like I mentioned above.

Hop this helps,

Andrew S

[Agent K]

Hello Andrew,

Thank you very much for the explaination and suggestions.  I will give the programable soft rest a try.   Oh, the links are extremely helpful also.

Regards,

Neil