Hi All
I have created a counter which is clocked by a 10MHz input into the NI-9401.
The VI I have created uses a second clock edge generated by a GNSS PPS signal at 1 pulse per second.
I'm trying to capture the high speed clock rate every second for a datalogging application.
When I have an input clock of up to 2MHz all is OK but above this the frequency captured seems to decrease (I assume this is probably aliasing).
I've attached my VI for comment.
I have 2 sections for edge detection which then cause the counters to increment.
I also have the PPS edge on a shift register so I can delay this by a single clock cycle to clear the counter used for input after this has been loaded to the indicator.
I thought the clock to the FPGA was 40MHz so did not expect this problem.
What could I be doing wrong?
Could anyone suggest a better way of doing this?
Best Regard Doug
