Synchronised Timing with Diuble pulse using PCI-6601

[JSherwood]

Hi,

I am trying to run a PIV system from Labview 8.5.1 using a PCI-6601 card to output the signals to the laser and camera.

This requires a line for the camera, one for the FPS (first pulse suppresion) and the one for the Q-switch.

The difficulty arises in the need for a double pulse on the Q-switch for double frame mode PIV.

The timing box I am using is not a NI one, and I only have access to 3 of the four counter outputs, otherwise i would simply use a T-junction BNC with two slightly offset pulses.

I do have access to a BNC-2110 timing box, but I believe this is not compatible with the PCI-6601 and do not have funds to purchase a BNC-2121 right now.

I have managed to create a double pulse by using one of the counters with a finite number of pulses set to 2, and then stopping the task, then running this in a timed loop. 

However, this then relies on the software, which will not be accurate enough for the application, and I cannot figure out how to get the timed loop to run from the 20MHz timebase from the 6601 card.

I may be missing something obvious here, or perhaps it is more troublesome? I am pretty new to DAQmx.

Thanks in advance

Joe

[Dominic.Walker]

Hey Joe,

So as I understand it, your looking to time your loop off the DAQ card's clock. 

In order to do this, you can simply place a "DAQmx Task Name" on the block diagram, select the clock you want from the drop down list and wire it straight into the Source Name of the Timed Loop.  The timing unit will automatically change from ms to ticks.  

However, judging from your complaint of the PC clock, I'm assuming your running this on a General Purpose operating system (Windows or Linux etc).  As the loop is still running in this operating system, triggering from the external clock will make little or no difference to the accuracy of the timing.  For more accurate timing, you'll need to run this on a real time operating system, which will give roughly 1ms accuracy, or an FPGA which will give you about 25ns.  

Let me know if this answers your question or not, and if you want more information on RT/FPGA options.  

Kind Regards,

[John_P1 · Accepted solution]

Dominic makes a good point about OS timing, but really the best solution is to use hardware timing whenever possible.

I put together an example that shows how you can implement multiple sets of finite pulses using the board's own timing.  It requires the use of two counters, but then again so does a Finite Pulse Generation (on the 6601).
Communities: Generate Multiple Cycles of Finite Pulses Using Two Counters


Alternatively, if you have another signal that you want to use to trigger each set of pulses (rather than specifying a rate for them to occur like in the above example), the counters on a 6601 are retriggerable so you could use the external signal to trigger the finite generation over and over again without needing to stop the task in software.

Best Regards,

John

[John_P1]

Almost forgot... there is also another way to get this to work with a single counter using Pulsed Mode since we only need two pulses.  We have a little less configuration options here, but from what you've described I think it will be sufficient.  Have a look at the following example and don't hesitate to let me know if you have any questions.

Communities: Generate Two Pulses Repeatedly Using a Single Counter

-John

[JSherwood]

Dear John,

.

Using the pulsed mode, didn't quite allow for the flexibility required, but the first example did the trick beatifully.

Many thanks for your help

Kind regards

Joe