beginner stuff: cRIO digital frequency measurement

[Jeff MHRT]

Hi,

This is really basic stuff, but I fear it's so basic that I've had trouble finding explanations that are at my level!  I've searched around the forums a fair deal, but if you have any threads to suggest, my ears are open.

Very basic task:  cRIO with a digital I/O module.  I will be using a magnetic switch to measure rpm of a motor shaft.  So i'm using one Digital output channel as a 5V source, and then that is connected to a Digital input channel through the magnetic switch.  With the switch closed, the input receives the 5V and registers a True.  With the switch open, the input registers False.  I've had that running without any problems.

My next task was obviously to measure the frequency of this signal going on and off as I pass the magnet by the switch repeatedly.  I looked up a bunch of the counter example vi's.  The Count and Period.vi example worked well, I had it running on my cRIO, where the FPGA generates a digital signal and then measures the period of that signal.  That was running, and then I tried to modify this code.  I removed the signal generation, in it's place I put an FPGA I/O node for my digital input from the magnetic switch, with the input node going inside the timed loop.  Outside of the timed loop, I put another I/O node for my digital output that would be a constant true for my 5V source.  In the Host vi, I removed any references to variables that I had deleted (mainly the control for the digital signal which I had now removed), and put an indicator to see if my digital input is receiving the True signal at all.

Once I've done this, the fpga vi compiles just fine, but when I click run on the host vi, there seems to be failed communication between my PC and the cRIO.  Sometimes i get the "waiting to connect" dialog and it eventually disconnects, or sometimes it doesn't disconnect, but I don't get any response from cRIO when I set the constant 5V source digital output to true.

My feeling is that I'm probably doing something fundamentally wrong.  My input/output nodes work fine, I can output a true to my magnetic switch, play with the magnet and see the input flip true and false as the switch turns off.  But as soon as I modify that and ad any kind of a timed loop to the VI, my cRIO stops responding.  Likewise, I can get the timed loop from the example project, Count and Period to run just fine, but as soon as I drop an FPGA I/O node anywhere in there, I run into troubles.

Sorry again if I'm really missing the boat, but I've been looking all over the various resources (forums, example vis, developer zone, google) and I'm just really stuck.  Thanks a lot for your help.

Jeff 

[Jeff MHRT]

sheesh... for some reason I can't seem to upload any files.  I have screen shots and the actual VI's, but I get an "unexpected error" every time i click "submit post" after having uploaded any files.  Hopefully we can work that out, or maybe I'll just have to give more details of how I've set things up in my vi's.

Thanks,

Jeff 

[Jeff MHRT]

Message Edited by Jeff MHRT on 12-19-2008 01:08 AM

[JMota]

I wonder if your timed loop is using too much CPU that is starving the service that communicates front panel controls and indicators back to your host machine, and that's why you are having those communication problems. Try reducing the period of the timed loop and see if that makes any difference.

[Jeff MHRT]

thanks for the reply!  Do you mean the period of the timed loop on the FPGA?  I wasn't able to see exactly how you changed the timing options on an FPGA timed loop.

[Jeff MHRT]

it looks like I'm doing something wrong, as it simply won't allow me to put an FPGA I/O node anywhere inside a timed loop on the FPGA vi.  I tried making a new vi, with a timed loop containing only a single read or a single write node in the loop and nothing else, and when I compile I get an error saying the I/O node takes one or more clock cycles to execute.  I've looked at other examples where I clearly see FPGA I/O nodes inside timed loops on the FPGA.  What might I be doing wrong then?  Thanks for your input.

Jeff

[StephenB]

Hi Jeff,

So timed loops on FPGA VIs act a little bit different. On real time targets you can set the rate of a timed loop say like, 1kHz. On an FPGA target, a timed loop acts as a Single Cycle Timed Loop (SCTL) where everything in the SCTL is executed in one 'tick' of the source clock. The default is 40MHz,  meaning any logic inside a SCTL with default settings must execute in 25 nanoseconds. The compiler will throw an error if you try to place too complex logic, or items inside the SCTL that it knows cannot execute in the desired time. Depending on your digital module, it might be able to execute in one tick, but chances are it can't. The IO node you are placing inside the SCTL is for a module that cannot execute an IO operation in one tick, and you get the error.

More information about SCTLs: http://digital.ni.com/public.nsf/allkb/722A9451AE4E23A586257212007DC5FD?OpenDocument

Setting SCTL rates: http://digital.ni.com/public.nsf/websearch/BF7CC6DC371D9DDB862570B9000A1FE7?OpenDocument

[Jeff MHRT]

Thanks a lot for your help Stephen.  I'll take a look at your links and let you know how I get along.

Thanks,

Jeff 

[Jeff MHRT]

Okay, I"ve had a go at this, everything seemed pretty straightforward.  I made a derived clock running at 2.5MHz, which seems to be the slowest speed supported by the hardware  (cRIO, 9102 + 9012).  However, there seems to still be some problem with my digital I/O node with respect to this new clock.  I'm using a 9403 Digital I/O module, and the impression that I get is that this module is too slow for even the 2.5MHz of my derived clock rate.  What's kinda silly in all this is that I only need to be measuring frequencies that are less than 1kHz!  This is going to be measuring rpm of an electric motor spinning at 4000rpm at it's absolute fastest.  Is there any way to get this digital I/O module to run in a timed loop?  Here's my latest error, I don't know why it's saying anything about my 9219 module in slot 3 since it isn't being referred to at all in the vi.

[StephenB]

Hi Jeff,

Here is a Knowledge Base that explains the clock domain error you are getting: http://digital.ni.com/public.nsf/allkb/0A933B88B50046B0862573D30007333E?OpenDocument

It looks like the 9403 module does not support the SCTL (LabVIEW Help » FPGA Module » CompactRIO Reference and Procedures » Digital Input Modules » NI 9403.... bottom of the page)

However, if you just want to control the sample rate, you can accomplish something similar with a while loop and a loop timer as pictured below. You also might find some good examples to work with in the NI Example Finder (Help -> Find Examples) under Hardware Input and output -> Compact RIO -> Basic IO