error 200019

[Junghwan]

Hi,

I'm trying to build an engine DAQ that uses encoder z and A as trigger and sampling. I'm using PXI 6123 and BNC 2090A. I set sampling rate at the maximum hardware sampling rate, 500kS/s, to increase buffer size. PXI 6123 can handle 500kS/s per each channel. Since it has external clock, I assume that the sampling rate shouldn't matter except for buffer size. Am I right? What could cause Error - 200019? I changed the encoder speed down to 600RPM, but no luck. When I switched to internal clock at the corresponding sampling rate, it works fine.

Please help me fix this. Thanks,

J

P.S. I wish could post a screenshot of my code, but it doesn't allow it for some reason. Sorry.

[Sarah_Y]

Hi J,

Error 200019 usually occurs due to a high sample rate or due to a low buffer size.  Here is a Knowledge Base article that explains this error in more detail and some possible causes and solutions for it:

http://digital.ni.com/public.nsf/websearch/A01AA72779C4604986257047007344EC?OpenDocument

Even though the clock is external, the rate specified in the task configuration determines the buffer size and other task parameters.

[Junghwan]

Sara,

Thanks for the answer. I followed the instruction and set the rate at the maximum hardware sampling rate, since the instruction says "the rate must be set to the greatest expected clocking frequency.". But, it still gives me the error.

Any thoughts? Thanks,

J

[John_P1]

Oh, I hadn't seen that KB before.  It isn't entirely correct...

-20019 is a hardware error that typically occurs if you try to sample the ADC faster than it is able to latch data into the hardware buffer.  So, the buffer size is usually irrelevant.  Really, the error message itself gives the best advice:

"Increase the period between ADC conversions.  If you are using an external clock, check your signal for the presence of noise or glitches."

Given that your clock signal is coming from an encoder, I'm certain that there are glitches on the rising edges that are causing each edge to register as multiple sample clocks, which is causing the ADC to overrun.  There is no digital filtering on the 6123 unfortunately, but you could use a re-triggerable counter task to clean up the signal (i.e. sample the analog input off of the counter's internal output.  The counter will only trigger once every 2 us):

With the counter example, you run the risk of sampling on the falling edge of the encoder which also likely has glitches on it.  If the encoder is running at a fixed frequency, you could find a CO pulse width that would overlap the falling edge to avoid sampling on the falling edge as well.

The better alternative would be to clean up the signal in hardware.  An external Schmitt Trigger would be my suggestion if you go this route.

If you were on newer hardware that supported it, I'd suggest to incorporate digital filtering.

Best Regards,

[Junghwan]

John,

Thanks for the example. But, I need to get voltage analog inputs, Your example seems only to allow digital countering to come in, since the DAQmx Create Channel block (Far left) is set at "CO Pulse Time". Is there a way to leave it at "AI Voltage" and add another block in front of the trigger block?

Thanks,

J

[John_P1]

Hi J,

I meant that you could use the counter's internal output as the sample clock for your analog task.  The counter would be triggered off of the external encoder signal.  The benefit is that the counter can only be triggered after the generation of a pulse has completed.  It's not ideal, since the glitches also probably occur on falling edges.  If you knew the encoder was outputting at a fixed frequency you could generate pulses long enough to cover both rising and falling edges and avoid glitches altogether.

However, assuming the encoder is outputting at a variable frequency, the best solution is to clean up the clock source externally. 

Newer DAQ hardware supports digital filtering which would also be ideal.

Best Regards,