Exporting Sample Clock problem

[Mystogan]

hi everyone,

I have a problem while using Dynamic Generation with exported clock.vi. The problem is, I'm getting 1/10 value of Vpp of clock signal when I route my clock to DDC CLK OUT. But when I route my clock signal to CLK OUT, its normal. (ex: I'm generating 1,8Vpp clock signal, exporting to DDC CLK OUT and I'm getting only 180mVpp). Anyone know about this?

regards,

Yan.

[snowpunter]

What hardware are you using for your DIO card and what are you using to measure the output of the clock?

[Mystogan]

hi,

I'm using PXIe-6544, and I'm exporting at the same time the sample clock into CLK OUT and DDC CLK OUT, and using BNC into scope. I think the problem is, I shouldnt wire them both at the same time to one scope. If I wire them individually, its normal. But if I wire them at the same time to the same scope, this problem happening.

regrads,

Yan.

[adigator]

Hi,

This seems to be very unusual behavior.

Have you ensured that your probes and scope are configured properly?

Probes normally have two divide options: 1/1 and 1/10

Are both probes configured at the same option?

Also try changing probes. Do you have the same behavior?

And last but not least ensure that the two channels of your scope are configured identically.

regards,

Adrian

[Mystogan]

hi adrian, thanks for response.

I dont think I know how to configure my probes. For my scope, I've used auto setting.

regards,

Yan.