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Resistor-matching in HSDIO 6544 and SCB 2162?

hey guys, just wanna make sure one more thing.

 

Have we been discussing just about digital OUTPUT all the time, or, this is also applied to the PXIe-6544 as INPUT either (for acquisition)?? I mean, when I'm acquiring digital data from my PCB to my PXIe-6544, would it be the same? There is 50 kΩ impedance on the INPUT channel parallel to ground (from the datasheet)?

 

regards,

Yan.

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Message 11 of 18
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Hi Yan,

 

From the spec sheet, yes the input impedance on acquisition is 50 kOhm.

Kyle A.
National Instruments
Senior Applications Engineer
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Message 12 of 18
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hi all,

just a quick question. How do I check my generated clock signal using HSDIO. I mean, I have generated a sample clock signal, and I can export this sample clock to DDC CLK OUT or CLK OUT. I can see the generated clock which I route to CLK OUT using oscilloscope easily. But, how do I see the generated clock using HSDIO board? I want to see them in Labview.

 

thanks,

Yan

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Message 13 of 18
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Hi,

 

On the CB-2162, with the VHDCI connector facing you, you will see DDC CLK OUT and STROBE on the left side of the PCB.  You can wire that up to another HSDIO line and sample at twice the rate, or get a BNC to two wire connector and view the signal on a scope.  There is very little difference between a clock on CLK OUT and a clock on DDC CLK OUT.  DDC CLK OUT is used for source synchronous applications, where the clock needs to propigate down the wire the same distance as the data lines to prevent skewing.

Kyle A.
National Instruments
Senior Applications Engineer
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Message 14 of 18
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hi kyle, thanks for your response.

 

I have tried using BNC from DDC CLK OUT into scope, and I could see directly the generated in the scope. But, can you explain a bit more about connecting the DDC CLK OUT pin to another HSDIO line and sample at twice the rate. I'm assuming, I need to connect the DDC CLK OUT pin to DIO0 (for example) then acquire the data using a program. Which program can I use to acquire the generated clock signal? Since I've used On Board Clk to generate clock, which source could I use to sample this? I've tried some examples provided by NI, but not sure which one I should use for this.

I have another NI card (PXIe-6674T), and I can generate another clock using this card, and connect it with SMA cable to CLK IN terminal on 6544. But when I run a program, somehow it wouldnt work, it tells me about voltage level from 6544 and 6674T are different. 

 

regards,

Yan.

 

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Message 15 of 18
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hi everyone,

 

I was experimenting with DDC CLK OUT signal. 40Mhz 1,8Vpp looks good. But when I put a capacitor 22pF parallel between pin DDC CLK OUT and GND, I got very low signal, about 1Vpp only. I mean, using 2m cable would have unwanted capacitance also, right? Would this be the same case when I generating my digital signal with 6544? I've taken a picture using my phone, but can't upload it properly. I'll try to upload it later.

 

regards,

Yan. 

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Message 16 of 18
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hi,

 

this is the photos.

 

a.png

 

Unbenannt.png

 

b.png

 

regards,

Yan.

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Message 17 of 18
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Hi Yan,

 

you are building an RC circuit and this always has a little voltage drop, normally the drop is round about 0,1 V

with your settings. You can calculate the voltage drop with this formula

Picture1.jpeg

And yes the circuits on our card have similar designes for digital lines and for the clock so it could happend you

can see the same behaviour on other lines.

best regards
Alexander
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Message 18 of 18
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