Sync 5105 external sampling clock with timebase divisor

[Groeg]

Hi there,

in a PXI setup, I am using a PXIe6556 HSDIO to generate a CLK and control sequence to run a CCD image sensor. In order to capture the image data, the sensor's analog output has to be sampled in phase with the rising CLK edges. I am solving this task by running a PXI 5105 scope with its PFI 1 as the external sample clock timebase source, which I wired to the 6556's CLK Out.

In general, this works fine. However, as I generate my CCD CLK from a "101010..." sequence on the 6556, the HSDIO CLK Out frequency is twice the CCD CLK. This means the 5105 samples both on the rising and falling edges of the CCD CLK. The easy solution to this is to discard every other sample, but this will waste half of my 5105's internal memory and therefore decrease the available sampling time.

I have tried to program the 5105's sample CLK timebase divisor to divide the 6556's CLK signal by two, but ended up in another problem: On every VI start, the divided sample CLK will lock by random either to the rising or the falling edge of the CCD CLK.

Anybody got an idea how to synchronize these two signals?

Thanks and best regards,

Georg

[ADagli]

Hi Groeg,

I would like to help you with your problem.

A similar problem has been discussed already here:

http://forums.ni.com/t5/Multifunction-DAQ/How-to-synchronize-Sample-Clock-Dividers-on-PXI-5105-and-P...

Best regards,

[Kyle_A.]

Hi Georg,

The issue you are running into is using a data line to generate your clock in respect to the onboard generation clock of the 6556.  The maximum toggle rate of any digital board will be half of the sampling rate of the onboard clock.

There are two ways of looking at this.  You can either synchronize by sending a reduced clock rate signal from the 6556, or you can synchronize the 5105 and 6556 across the backplane.  Unfortuantely, at this time, the 6556 does not support TCLK synchronization.  I will try and explain what I believe are alternative solutions: 

You can use a data line to send a clock to your 5105 so that it can sample at the same rate as the data.  Then, you will conserve it's onboard memory as much as possible, but at the cost of losing a data line.  However, if you have one free, it would be convenient and all that would be required is the proper breakout to get the signal to your digitizer.  

Synchronize both modules to the backplane PXI_CLK10, then use the Data Active Event from the 6556 to trigger the 5105.  PXI_CLK10 is on the backplane of all PXI chassis, and can act as a reference clock to phase lock the modules together on a common source.  To obtain a higher stability clock, you would need a Timing and Sync module to substitute the PXI_CLK10 clock with its onboard clock.

A third option is to split the clock going from the 6556 to the 5105, and take the third line to your DUT.  That way, all three have the same frequency and phase, with just the added path delay from the cabling.  

There may be other options, but these are a few to hopefully direct you down the right path for the solution that is the most useful for your application.  Let us know how else we can help, thank you.

[Kyle_A.]

Just a quick clarification, I meant that in this case, TClk will not be a solution.  For the PXIe-6556, TClk is supported for synchronization between other 6556 devices.  The 6556 at the moment cannot TClk with any other device.  Thanks.