Will the PXI-6561 board work with serial LVDS data clocked at ~70 Mhz?

[NeilY]

I currently have a PXI-6561 card and an unused SMA-2164 board (accessory board for the 6561).  We are looking to connect a camera that outputs data via Serial LVDS, that is clocked at 73.636 Mhz.  However, can the PXI-6561 data lines handle data at that speed?  From the NI-6561 Specifications document I see that the clocking can be run that fast, but I don't see anywhere if the data lines can run that fast. The 2164 board looks like it's made to read the data in parallel (16 bits at a time), but we're runnning the camera serially.  I'm not an EE so I just wanted to know if we are barking up the wrong tree before we get the wiring/connectors/termination resistances made.

Thanks,

Neil

[Tunde_S]

Hi Neil,

I believe the KnowledgeBase, here, provides the solution for reading your serial bitstream.

[Kyle_A.]

Hi Neil,

You can handle data at that speed, but you will need to bring in an external sample clock at that frequency to do it.  The onboard clocking architecture is divide by N, meaning that at higher frequencies, you cannot hit most of the fine resolution clock frequencies that you may be looking for.  We do have several single ended HSDIO boards with fine resolution clocks (6544,5,7,8 and 6556) but the 6561 does not.  

When it comes to sampling, if you bring in a clock that is 73.636MHz, you can use that as your acquisition clock, and what that means is that for every rising edge of that clock, you will receive a sample.  If your data is coming in faster, say 8 bits per word, and the words are running at 73.636 MHz, that means your data is running much faster, and the deserializer mentioned in the previous post would have to be used to achieve that rate.  Or, we do offer a FlexRIO solution in the NI 6587 that can clock data at 1 Gb/s.  

I would reference the help file as much as possible for more information about the board, and you can find that online here.