Building Lock In Amp in FPGA

[Joonam]

Hello,

I'm interested in building Digital Lock In Amplifier with NI 5733R. I read this and realized it might help me.

A Digital Downconverter for the NI 5734

http://www.ni.com/example/31525/en/

But I stucked at certain points.

1. How to insert an external TTL signal into the DDS Compiler? Shouldn't I do this for measuring phase between the signal and the Reference TTL?

2. What it means the "Phase increment programmatically" in the DDS Compiler IP Pallette?

Do you guys have some ideas or suggestions?

Best Regards