Re : Re: Re : CLK IN NI PXI 5922

[laulaurent]

Hi,

I'm using a 5922 digitizer with clk input and i have a problem.

My problem is simple: I could not phase lock to the external reference clock.

My CLK IN signal is a -250 mv:+250 mv square signal at 2Mhz (from low frequency generator) (this signal match with the spec).

My ch 0 signal is a random signal according to the spec range.

When i use Ni-Scope Express in LabView, my parameters are :

-> Range 2V

-> Coupling AC

-> Offset 0

-> input impedance 50 Ohm

-> Probe attenuation 1

-> Bandwith 0

-> Sample rate 2M

-> Record length 1000

-> N samples

-> Trigger type Edge

-> trigger source External trig

-> slope Positive

-> Coupling DC

-> Ref position 0%

-> Level 0V

-> Max time 10s

-> Delay 0s

-> Reference clock source : clock in

My error is :

"DAQmx Error -200245 occured

Measurements : PLL could not phase lock to the external reference clock.

Make sure your reference clock is connected and that it is within the jitter and voltage spec...."

Dont care about external trigger, it work fine !

I'm also using a NI example : niScope EX external clocking (i was just changing sample clock timebase source & rate by ref clock source & rate) and it dont work too.

and there is no signal on CLK OUT at any time.

What can i do, i'm locked with this problem ?

Thanks !

[EBL]

Bonjour Gendre,

The 5922 has a VCXO (voltage-controlled crystal oscillator) that it locks to your source. This VCXO can tune only over a range of +/- 50 ppm or so. That means your clock signal must be within +/- 50 ppm of 2 MHz exactly (2 MHz +/- 100 Hz) in order for the VCXO to lock. Do you know the frequency accuracy of your signal source, or can you give us the manufacturer and model number?

Cheers,
Ed L.

[laulaurent]

I have test with a +/- 100 Hz value and it work !

but i really need to drive the card at about 943khz, 1.88Mhz, 2.83Mhz ....

what about the RTSI clock on the card ? how it work ? (is it on th 9 pin mini circular DIN ?)

I cant use ch1 trigger because my samples are not sync with what i want !

[EBL]

Hi, Gendre.

Unfortunately, because of the oversampling design of the 5922, the ADC always has to have a 120 MHz master clock. That means you can't feed in an external clock for the ADC - the 5922 can only lock its own 120 MHz VCXO to an external clock. And that external clock must be within +/- 50 ppm of either 1 MHz, 2 MHz, 3 MHz, and so on, up to 20 MHz, in order for the VCXO to lock.

There is some choice for actual ADC sample rates, but they are all integer divisions of 60 MHz and are derived from the 120 MHz clock. So, for example, you could have 60 MHz / 64 = 937.5 kHz, 60 MHz / 32 = 1.875 MHz, or 60 MHz / 21 = 2.857 MHz, but of course those are not the exact frequencies that you need.

I wish I had better news for you, but those are the limitations of the hardware.

Cheers,
Ed L.

[laulaurent]

Hi,

For example 60 MHz / 32 = 1.875 MHz is a sampling frequency (into the 5922) and i really need to be synchronize with my external clock  (so, not in intern).
Im now investigate on an alternative clk in (1Mhz or 2Mhz)  and i try to fix some problems like "PLL was unlocked" when i use my new clk and an edge trigger or " this device does not support RIS", ...
Its a little fastidious cause of parameters i have to take care.

But the main important thing on my work is the voltage precision.
In 20 bits, i have an important difference between two values for the same voltage input (verified by a scope) -> approx. 30 mV.
For a 0 : +250 mV signal with a 1 mV noise, its annoying !
Maybe, the antialiasing filter into the card is a problem for my measure.

Thanks for helping me, its not simple to drive this card for what i want !

ps : tomorrow i will post my VI.

[laulaurent]

i have resolved all problems but i can't resolved my voltage precision problem because of the antialiasing best step response filter (Approx. 400 ns is too high for my system).

If u want u can see my futur post in the main sub forum high speed digitizers !