10-19-2018 12:02 AM
Hi,
I am trying to design a filter in a USRP RIO (say RIO0) which will receive a Mixed Signal from other USRP RIOs (say RIO1, RIO2), do the filtering in RIO0 and transmit back the filtered signal to RIO1, RIO2. So, how can I design a filter in a USRP RIO with RX and TX in the same VI using LabVIEW Communication Design Suite 2.0?
Mirza
Solved! Go to Solution.
10-19-2018 03:23 PM
Hey Mirza,
If you are using the NI-USRP host based driver, you'll only need to modify one of the examples to get the functionality that you need. If you look at the Full Duplex USRP example, you would need to modify the example for the channels you'd like to use, take the received data and filter it, then write this filtered data to the USRP Tx.
If you want to implement this on FPGA, take a look at the USRP RIO example project. To modify this example, you'll need to take the IQ data from the FPGA I/O Rx Input nodes, perform the filtering, then wire the data to the FPGA I/O Tx nodes. You may need to implement the filtering in a different clock domain to get the performance you need.
10-19-2018 06:02 PM
Jon,
Thank you for your prompt reply! I will try the Full Duplex example.
Mirza