USRP RIO Dataclock configuration

[wheberth]

Hi all,

I´d like to know what is the configuration needed to confiure the dataclock. 

I have started a blank project, and the Dataclock (x1 x2, etc..) doesn't work.

I know that I can create another clock with tha same frequency derivatted from board clock. I am also aware that I can start from the streaming example project. But what I really want is to understand exactly what needs to be configured to have this clock working.

There are some configuration nodes that are intended for clock configuration but the documentantion available for those blocks do not explain the nodes in context, just describes its inputs and outputs.

[National_Burritos]

Hi wheberth,

Can you clarify what you mean by "not working"? Do you get errors when programming? Or does it not compile?

Thanks!

Rahul

[wheberth]

Running in simulation mode the code works properly,  the compilation finishes with no error, but when the bitfile is deployed to the FPGA, the code do not run. Is not possible to get any response from the hardware.

If I create another clock with the same frequency but derivated from the "board clock", and recopile, the FPGA code runs properly.

[lferreira]

Hi Wheberth,

What USRP RIO are you using? I suggest you try the example Xilinx IP FIR Filter available in Programming FPGA>>Clock Driven Loop and change the clock border node input to Dataclock and check it is runs properly.

Thanks..

[brooksprumo]

The Data Clock is configured by the host, and requires some logic on the FPGA to facility its configuration. Without this logic, the Data Clock will not be turned on.

FPGA VI:

You must have the 'required' section of code in your FPGA VI. This code is part of the Sample Project, and you can also use the USRP RIO palette to access the required section.

Project:

You must have the associated DMA FIFO that is used by the FPGA VI above.

Host VI:

You must call niUsrpRio::Open. After this VI runs, the Data Clock will be up and running. 

[wheberth]

Hi lferreira, I am using USRP RIO 2952R 120MHz. If I use the examples, the dataclock works properly.

My goal here is to understand exactly what (programming) is needed in order to get this clock working.

[wheberth]

brooksprumo,

I can't recognize the blocks yo are describing and the interface image you sent.

I am using LabVIEW Communications 2.0. What software version are you using?

Thank you very much brooksprumo and lferreira.

[brooksprumo · Accepted solution]

Oh, you're in Comms 2.0. My images were from LabVIEW 2016. Let me look through Comms 2.0 and get some screenshots. The code will all be the same, but the lvproject settings will look a bit different.

Again, the best thing to do is start from the USRP RIO template projects and create new VIs from that.

1. Start from a template
   • 
2. Add the REQUIRED section to your FPGA VI
   • 
3. Call niUsrpRio::Open in the Host VI
   
   • 

[wheberth]

Thank you very much, I will try and let you know how it worked.

Best regards

[National_Burritos]

hello!

Basically, what you need is the "FPGA plumbing" in the Sample Streaming Project. What brooksprumo showed was a little VI in LabVIEW 2016. In Comms 2.0, I would insert the loop with your IP in the the Sample Streaming Project (Projects>>Select your USRP -RIO target). In the FPGA VI there, you will notice the configuration loop present as mentioned, which starts the actual data clock.

Cheers,

Rahul