VHDL code integration?

[silvio.baccari]

Where I can found a functioning sample code for importing VHDL code into myrio? Do you know if I can use Matlab HDL coder to produce compatible VHDL code?

Best regards,

Silvio Baccari

[[dk]]

Hello Silvio,

Are you wanting to use a myRIO with LabVIEW Communications? Unfortunately the myRIO is not supported with LabVIEW Communications.

However, we do have a few examples of integrating VHDL code via CLIP with a myRIO. This might be a good starting point:

https://decibel.ni.com/content/docs/DOC-30484

[marioalves]

Hi!

I read the "How do I import 3rd party FPGA IP into a LabVIEW Communications FPGA VI?" document and managed to run the example "DemoClipAdder". That was very helpful, thanks!

However, manually generating .eip files seems to be a tricky task, requiring firm understanding of the IP-XACT XML schema with high probability for human mistake. Therefore, is there an automatic procedure for generating the .eip files? 

I tried using Kactus2, Design Player (vhdl2ipxact) and Xilinx's Vivado tools, but none of them seem to work. I mean, they create .xml files (which I renamed to .eip when importing into LabVIEW Comm.) that are similar to the .eip files. Among the differences between these files, the absence of the XML-tags <spirit:vendorExtensions>, <chrec:portExtension>, <chrec:highLevelType> and <chrec:portCategory> in the .xml files seems to be, maybe, the major reason why it doesn't work. 

Anyway, I added a file generated by Design Player to this repply and the original .eip example in case someone would like to compare them.

If anyone has a hint or a suggestion on this topic it would be very helpful!

Thank you for your attention,

Mário

[Ben_Co]

Hi Mario,

Unfortunately there isn't a way to automatically generate an .eip files. You are correct, it is a tricky task, and requires quite a bit of IP-XACT understanding. Hopefully someone with the required experience can some provide some insight regarding those files. 

Regards,

BeenCoughin

[Victor.F]

Hi there

I believe we will have an easier way to integrate IPs in the future. Stay tune on this.

So for now, I attach a documentation that will help you understand how to create the proper IP-XACT so that LV Communications recognize

the interface.

Also, for more examples on how to do this, feel free to walk through the Sample Projects (the ones that includes some FPGA code like USRP-RIOs, RF FAMs)  in LV Communications, where you'll find

multiple IP integration (look in the System Designer, under the Target's References to easily find them).

Let us know if that helps !

Regards

Victor F.

[marioalves]

Thank you Been and Victor for your comments.

I managed to edit the examples with some modifications and I also created some .eip by modifying the .xml generated by one of the tools I cited.

These EIP worked fine, but doing this manually is really an unpleasant task. 

The document "To use IPIN in CSDS 1" was helpful for me to understand some things that were not very clear. 

Maybe I'll try to write a script that generates the .eip automatically to help me for now

Thanks again

Mario

[Victor.F]

Hello Mario

Good to know that you were able to move on!

Feel confident that we will provide later this year, a path that will automated all that.

Thanks for those feedback.

Have a nice day.

Victor

[Julianosf]

The informations given before were very helpful to integrate a VHDL file on my LabVIEW Communications project. Thanks for everybody!!

At this time I have a additional question that is: how I can integrate a Vivado's IP on LabVIEW Communications project?

I´m not sure about the files that must be mentioned in the .eip file to allow import the Vivado's IP on LabVIEW Communications. Additionally, I don't know if is necessary generate the IP with some specific configuration.

Thanks in advance!

Best regards,

Juliano

PS. At this time I´m trying to add a FIFO IP generated by Vivado's FIFO Generator just to understand and validate the importing process.

[Victor.F]

Hello Juliano

Here are some hints.

I guess you'll be able to import what's currently supported by LabVIEW:

http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/integrating_hdl/

My advise would be that you generate the proper netlist for your IP , this one will be used for synthesis.

Use a dedicated <sprit:view>, for synthesis in your .eip.

If you want to simulate the IP in LabVIEW Communications, then you'll also need to generate a functionnal VHDL simulation representation of the design.

Also use a dedicated <sprit:view>, for simulation this time in your .eip.

If you're still struggling with this, please create another post, as this one is marked as resolved.

You'll have better chance to find help this way.

Regards

[Phy_comm]

Dear Victor,

I am using version 2 of CSDS and did implement simple ip exports from Vivado but am stuck in ones with multiple VHDL files as ports are not recognised here.

Please have a look. https://forums.ni.com/t5/LabVIEW-Communications-System/Main-Simulation-entity-HLD-IP-from-VIVADO-HLS...

https://forums.ni.com/t5/LabVIEW-Communications-System/Importing-IP-issue-HDL-port-not-recognised/td...

I have attached working and non working files.