Many times I create a new FPGA VI to run from the same project and it needs an extra memory block or maybe a new I/O pin, so I add it in the project for that new VI. Meanwhile all my other FPGA VIs that don't have anything to do with that added piece will now need to recompile (very time consuming).
It would be nice if those VIs did not need to recompile since that new memory block, I/O, or clock are not being used in the old already compiled VIs.
Brad Remenak
Certified LabVIEW Architect
