LabVIEW FPGA Idea Exchange

Post an idea

Visually detecting the presence of CDC (Clock Domain Crossing) in LV code is only semi-intuitive. It is required to check the set clock of the SCTL and / or follow the wire to the clock constant / control in order to understand in which clock domain the code is running.

I suggest having the option to automatically colour the background of the SCTL according to the clock being used.

Obviously, this won't work well over VI borders, but at least the option to have it vivible on the same diagram is already a nice step towards better visibility of this really important part of LabVIEW FPGA programming.

An option to actually couple a colour with any given clock constant / control for SCTLs would be an addition I personally would very much appreciate.

Yes, these colours are probably a bit extreme, but given the fact that I'm dealing with so many individual processes, it is preferable to having to constantly follow all the wires or investigate all of the SCTL settings.

View All (1)

As somewhat an opposite request to this idea

https://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Ability-to-define-datatype-of-Registers-FIFOs-from-code-without/idi-p/3123936

I would like to show some pertinent information to the configuration of certain primitives in FPGA code.

The ability to turn this display on and off just like a label would be very welcome indeed. I'd always have it visible.

I just spent two days tracking down a bug which ended up being an under-dimensioned Block RAM instantiation (and how BRAM indexing works, just throwing bits away instead of coercing the read/write index), something whose configuration is completely hidden from view. Why can't we have some visible elements to show the size of a Block RAM and the Datatype (FXP would do for any given FXP type). Same goes for FIFOs, whether a FIFO is 16 elements or 8192 elements deep is a very important piece of information. And of course I mean only the primitives which instantiate the resources, not FP references for these items, even though the datatype of these would also be a very welcome addition.

View All (2)

It would be nice to have control of clock.-independent assignments of signals from I/O nodes (without synchronising registers) without having to specifically having to use a clock for the connection.

Image says it all.

We have tried using a static assignment on the top-level diagram, without using a SCTL but it appears that does not work. The example links within a single CLIP, but the idea is aimed at actually doing some connections between multiple different CLIPs without the need for a specific VHDL wrapper for each individual configuration.

View All (1)

FPGA resource utilisation visualisation

How amazing yould it be to have the ability to visualise resource usage on a FPGA target using a similar view to that shown above (courtesy of Windirstat)

I only recently shaved a significant portion off my FPGA usage by finding out that I had a massively oversized FIFO in my code for almost a year without noticing. I feel that this kind of visualisation (with mouse over showing what is actually occupying the space) with differentiation between Registers, LUTs, BRAM, DSPs and so on would greatly aid those of us trying to squeeze as much as possible out of our FPGA designs.

I think providing this information based on the "estimated resource utilisation" i.e. before Xilinx optimises stuff away would be OK. I'm not sure if the final resource utilisation can be mapped as accurately in this way.

It would also be nice to see CLIP utilisation and NI-internal utilisation at a glance as this is apparently hugely different between targets.

Shane.

Allow Type Cast in FPGA

View All (2)

Logic Operators and Arrays

Auto-Migrate to New RIO Target

I just manually transferred a fairly large LabVIEW FPGA project from one target to another (7965R to 7966R). It would be nice to be able to click on the RIO target in the project and have an option to "Migrate to New FPGA Target" in the context menu. The menu would open a new dialog where you could select the new RIO target and then it is automatically added to the project and populated the VIs, FIFOs, derived clocks, memory blocks, etc. from the original target. The user can choose whether or not to delete the original RIO target.

This would also make it very easy for users to transfer sample code from the LabVIEW Example Finder to the correct FPGA target (insead of having the folder labeled "Move These Files").

Single cycle timed loops are a huge performance enhancer in LV FPGA. We learn to use these very prolifically in and around our code to save precious FPGA space, yet the BD representation of the SCTL is the standard Timed Loop structure, with both the Left and Right "ears" visible as well as the conditional terminal.

I propose that the SCTL be given it's own representation on the block diagram, one without the "ears" and without the conditional terminal (by definition it only runs once). This will promote much cleaner looking FPGA code and more readable diagrams.

View All (1)

Incremental Compile LabVIEW FPGA

Hello all.

It is time-consuming that we have to compile all LabVIEW FPGA code even if there is tiny little change on FPGA code.

I understand there is sampling probe, Desktop execution node and simulation tools to reduce such time.

Our customer in Japan, would like to use incremental compile function also on LabVIEW.(Please see below)

I agree his opinion.

http://www.youtube.com/watch?v=9v50uCVdW3o

What do you think?

Eisuke Ono

Application Engineer at National Instruments Japan.

View All (4)

LabVIEW NXG had the ability to create a resource file. Though I cannot find the help reference for this I will describe the functionality below:

Right now the Target Scoped FIFO, P2P, DMA-FIFO, Memory, Handshake Items, Registers, Clocks, etc are all stored as part of LabVIEW Project (lvproj) file.

If want to port to a new project file or target I have to copy/paste. This is not a big deal and works well. However if I update one project's configuration I have to re-copy/paste. From a configuration management perspective I cannot ensure the configurations are always the same. With larger, multi-FPGA projects this becomes critical.

It would be great to have a file that holds all of these resources to allow for easier portability and configuration management.

View All (1)

Select in SCTL

Initially I looked around for my previous idea here: Selecting between two I/O refnums not allowed because I thought it was the same and intended to post a comment to that, but I see that was a bit more specific.

This seems like a more allowable case - why is A forbidden and B perfectly ok?

Select node in SCTL

Case Structure to choose between two values based on boolean input

Here A is forbidden (at Intermediate file generation - so perhaps this would help: Unsupported nodes inside for loop within SCTL should result in a broken VI (NXG != Already Implemented really...)) but B is compiled with no problem. I really don't see why Select of two integers is different to a Case Structure with two integers input, a boolean case selector, and an integer output from the two inputs...

As an idea rather than a rant, I'd like A to be possible.

Better FPGA FP Control Selection

When there are many controls on the front panel of the FPGA, selecting the control from a Read/Write Control node in the host can become a pain. It is one very large list of controls on the front panel of the FPGA. This list has no scrollbar, no browse, or search feature, and no obvious way of grouping controls.

Here is one example of a front panel, and a video showing how long it takes to scroll through the list of contorls.

And here is the video of me scrolling through the controls: http://screencast.com/t/PLzptTwq58aw

There is plenty of room for improvement. Here are just a few ways I think NI could make this better.

Browse and Search

When using a Property Node, or Invoke Node, the very top option is to "Browse..." From here a list of all properties, or methods can be seen in a resizeable window. Here you can also search, and sort alphabetically. The Read/Write Control node could have similar functionality making selection of controls easier.

Front Panel Selection From FPGA

There could be an option for creating a node by selecting the controls on the front panel of the FPGA. A solution that may work today, is to select the controls, then invoke a custom QuickDrop command that creates the node and puts it in the clipboard so it can be pasted in the host VI. If this were to become an option, I'd hope there is a way to combine two nodes into one, by concatenating the controls of one onto the other.

Front Panel Selection From Host

Lets say you already have the Read/Write Control node on the host. There could be an option by right clicking that would open a new window, showing a static image of the front panel of the FPGA, which the user could then click on. This would be great because the developer probably already knows the control they want based on the front panel location. I don't know how possible this is because you could load a bit file which won't have any front panel information.

Easier Grouping of Controls

Right now there is a way to group controls of an FPGA. This feature is never talked about, and doesn't work on dynamic bit files. Here is a discussion where I describe the steps to make controls grouped on the host. Still this isn't supported on all FPGA setups, and you have to conform to a specific naming convention. Why can't controls that are grouped on the front panel, just be grouped in the host?

This idea exchange is really for any kind of improvement to the FPGA control selection.

When we try to compile timing critical FPGA application, if might be failed because of timing violation.

But if it missed only a few nanoseconds, recompiling might resolve the error as below.

Resolving Timing Violations on the FPGA

If your failed compilation misses the required throughput time by only a few nanoseconds, try rebuilding your bitfile. Each build of a bitfile does not always produce identical results on the FPGA, so rebuilding sometimes resolves minor timing violations.

In most case, compilation might require much time and it's difficult to take quick action after they found the aborted compilation result.

It would be great there is an option which allow automated recompile like below.

Of course the compilation completed, it wouldn't try recompile. Only failed, try to compile again.

** -------------------------------------------------------------------- **

Enable Auto Recompile [ * ] Number of Retry [ 4 ]

** -------------------------------------------------------------------- **

I have several FPGA projects that require significant compile time (up to 1.5 hours), and for that I am thankful to have my compile server running on a separate computer.

The issue comes with the seven Pre-Compile steps that occurs before LabVIEW sends to the code to the compiler. On one particular project this action alone can take up to 35 minutes during which time I can do nothing on that machine.

I would like to see much of this precompile time moved from the development environment to the compile server. There already exists a mechanism for updating the user with the compile status so those precompile errors could be annunciated in a similar fashion.

Get the development system back online as quickly as possible.

View All (1)

What do you need our team of experts to assist you with?

Request a quote Find the right product Place an order Get support on a product

How can we help?

Please enter your information below and we'll be intouch soon.

This field is required

Preferred communication method

Email Phone call

What do you need our team of experts to assist you with?

Request a quote Find the right product Place an order Get support on a product

LabVIEW FPGA Idea Exchange

Option to colour-code SCTL backgrounds according to Clock selections

Show some important resource data on FPGA items (Block RAM, FIFO etc.)

Concurrent assignments on the LV top-level diagram

Please add FIND ALL functionality for Memory, Register, and FIFO items

Create single FPGA I/O node instead of multiple

FPGA resource utilisation visualisation

Change the font in the Xilinx Log window to fixed width

Allow Type Cast in FPGA

Logic Operators and Arrays

Auto-Migrate to New RIO Target

Simplify the display of Single Cycle Timed Loops in LV FPGA

Allow Cluster and Array Transfer Types for DMA Streams

Import export IO user label to and from excel in FPGA project

Incremental Compile LabVIEW FPGA

Add ability to have resource files in LabVIEW FPGA

Select in SCTL

LabVIEW FPGA properties Custom Control Data Type dialog boxes need to show the path and name for the last configured .ctl

Better FPGA FP Control Selection

Enable "Automatically retry the compilation if Timing Violation Error occured" option

Minimize Pre-Compile actions on the local computer when compiling FPGA code