LabVIEW FPGA Idea Exchange

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Tepig

Enable "Automatically retry the compilation if Timing Violation Error occured" option

Status: New

When we try to compile timing critical FPGA application, if might be failed because of timing violation.

But if it missed only a few nanoseconds, recompiling might resolve the error as below.

 

Resolving Timing Violations on the FPGA

If your failed compilation misses the required throughput time by only a few nanoseconds, try rebuilding your bitfile. Each build of a bitfile does not always produce identical results on the FPGA, so rebuilding sometimes resolves minor timing violations. 

 

 

In most case, compilation might require much time and it's difficult to take quick action after they found the aborted compilation result.

It would be great there is an option which allow automated recompile like below.

Of course the compilation completed, it wouldn't try recompile. Only failed, try to compile again.

 

** -------------------------------------------------------------------- **

Enable Auto Recompile [  *  ]   Number of Retry  [  4  ]

** -------------------------------------------------------------------- **

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2 Comments
Terry_ALE
Active Participant

For such borderline designs, I have several duplicate build specifications and run them all with the hope that one of them pass. 

 

There is an undocumented API in the LabVIEW folder which one could automate LabVIEW FPGA builds.

 

Overall I support this idea whether it is adding to the compile settings or documenting the API.

 


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
Tepig
Active Participant

Thanks Terry for your comment. I didn't know there is an API : ) I hope it will be implemented into compilation dialog window.

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