FPGA FIFO and Memory Editor

[A_Ryan]

I have been working with FPGA for quite a while, and realized that manually opening and editing DMA, Target Scoped, P2P, VI scoped Memories, and project scoped memories can be very tedious and time consuming.  Wouldn't it be great if there was a way to edit FPGA FIFOs and Memories from a single place.  This notion gave birth to the FPGA FIFO Editor and FPGA Memory Editor.  These editors would give the ability to see, create, remove, and edit FIFOs or Memories for that specific project (list both project and VI scoped items).  Furthermore, their could be some additional logic built into the Editor that would alert the user when they have tried to configure something incorrectly (for instance an R Series target only has 3 DMA FIFOs, alert the user when they have configured more than that).

Listed below is  a mock-up of the FPGA FIFO Editor.

[Dragis]

I'm curious, how many of those settings do you normally modify from the defaults? Would it be better if LabVIEW FPGA provided a way for you to create these resources from the diagram, wire up whatever configuration you care about, and then infer the rest from the code.

For instance, with a DMA channel the tool can in general infer the type of the channel from the data type you wire to the Write method. LabVIEW could similarly add a "type" terminal to the Read method so specify what you expect to read.

[A_Ryan]

Personally, I end up making several changes during the design process or I forget to set something correctly.  This usually gets copied to several other locations on the BD.  Even if I don't end up editing the defaults, changing the FIFO names once they are created is time consuming process (especially for a typo).