Tell us why an FPGA needs to be recompiled

[JonP]

The error "You must recompile the VI for the selected target" appears for reasons that, to me, are often obscure or even inexplicable. Recompiling is, as we know, painful. It would be good if the error message included the reason(s) for refusing the existing bitfile, since then I may be able to work out how to stop it happening.

I understand the message comes because LabVIEW decides there are "dirty dots" associated with the bitfile, what I would like the error message to tell me is which dots are dirty and why.

[ALST]

Amen.

[crossrulz]

ALST, If you like the idea, you need to give it a kudos (the start next to the title).  Just a comment will do nothing to help NI R&D to see the support for the idea.  Kudos are simple numbers and that is what NI uses when prioritizing ideas.

[ALST]

Yes,I gave you kudos this morning!

[GregSands]

Yes please, and especially if LV can give an option to override this message.  The most annoying case is after getting this message from a VI that uses a given BuildSpec, then attempting to Build the BuildSpec, LV gives the message "The bitfile is up to date with the build specification.".  The FGPA code has not changed, or been saved in the meantime - perhaps the Project file has been saved, but without any changes to the FPGA section.

[JCC_(SK)]

I agree with you.

I am using this work around for top FPGA main VI to not be mark as modified when opened (and then recompilation is required):

When I am finished with code modification then I set main VI Properties ->  Protection -> Locked (no password), save it, recompile it.