9871 problems in hybrid mode

[Guenter]

Hi everyone,

I have a 9024/9113 with a 9871 and other modules. When I configure it in scan mode, everything is fine. When I configure it as FPGA Hybrid, add FPGA code and run it from the project, still everything is fine. But when I compile it, download and restart, I get VISA error -1073807343. The 9781 and other modules are all run in scan, I only use FPGA to get the chassis temperature.

To summarize: ScanMode / run -> OK, ScanMode / download -> OK, Hybrid / run -> OK, Hybrid / download -> error

Did anyone experienced similar behavior?

Thank you and greetings Guenter

[iCan'tBerrPuns]

Hello Guenter,

In order to get a better idea of what could cause your problem, I have a few questions.

1. You listed two cRIO chassis in your post; are both of these cRIO chassis part of your LabVIEW project?

2. When you say that you “compile [your code], download and restart,” do you mean that you:

• Compile your FPGA code onto the FPGA of your chassis
• Deploy your RT code to your controller as a startup executable

Essentially, what is not clear to me is what you mean by “download”.

3. Do you have the following drivers installed on your cRIO chassis: NI-RIO, NI-Serial RT and NI-VISA? You will need these for serial communication.

4. The VISA error that you experienced can occur for many reasons. If you are trying to read/write from the serial port on your cRIO chassis, I recommend that you take a look at the following KnowledgeBase.

Error -1073807343 When Reading/Writing to Serial Port on CompactRIO (cRIO)

http://digital.ni.com/public.nsf/allkb/570B021DEBA08213862579990074F9D1

5. As your NI 9871 module is a Serial Interface Module though, you are most likely using it for serial communication. This module requires an external power supply in order to operate; are you providing it with 8-28 VDC?

6. What version of LabVIEW are you programming in?

7. I recommend that you compare the code that you have written for serial communication with the LabVIEW example project “NI-987x Serial Loopback.lvproj”. Deploy this code to your target and see if you still get the error message you were originally seeing. It is possible that there is something within your program that cannot execute once it is deployed to your RT target.

Please send your responses to these questions whenever you can; also, please let me know the outcome of deploying the example project to your cRIO.

Regards,

[Guenter]

Hi, Gabby

to clarify things:

- I am using LV2013SP1.

- the 9024 is a controller, the 9113 is an FPGA chassis (National Instruments Applications Engineer ...?)

- Yes, I do use the serial communication module for serial communication and I do supply it with power, just as I did the last 5 years that I am using this module.

- What I mean with "download" is to compile the FPGA code (if applicable), build the RT code, set it as start-up, deploy it and restart the cRIO. In contrast to simply run the VI from the project. In both cases code is transferred to the cRIO and executed on the cRIO and though with first method I get an error, with second not.

- If the chassis is configured in scan-mode, both (deploy and run) work the same way, as they usually do.  If the chassis is configured as FPGA (with an FPGA code built and used and the 9871 in scan mode) I get the problems.

- Since the code is running as expected when I run it from the project (and my 18+ years LabVIEW experience) I do not think that it is severely wrong. However, I so far used cRIO mostly in pure FPGA mode sometimes in scan mode (with the 9781), but  not as hybrid, that is why I am asking if there is something specific that I overlooked.

thank you for looking into that, greetings, Guenter

[natasftw]

While she likely could have found you're working with a controller/chassis combo, it's not entirely surprising one of the AEs isn't familiar with hardware old enough they likely hadn't started college when it was purchased.  The snark probably wasn't needed.

With the newer cRIO devices, you can download the FPGA bitfile directly to the device.  The point of this is it allows the FPGA to get into a good state immediately rather than waiting for the RTOS to boot up and load the bitfile into the flash.  Have you tried this option?  I'd expect it works on the older devices as well.

With one of the AEs posting in your thread, it'd probably help to throw together a quick project.  It sounds like you've got working code.  Do you have a simple loopback test that works well with scan you can post?  If so, it can be opened up in newer versions for testing.

Is it safe to assume you're using Open FPGA Reference VI on your RT and linking to the FPGA VI?  Or, are you linking directly to the bitfile?

Citing your experience in different places doesn't really help.  It sounds like you might be finding a bug.  But, there isn't any experience level that's immune from making mistakes.  Please focus on the question at hand rather than trying to tout experience.

[Guenter · Accepted solution]

Hi,

I did not mean to offend anyone here, I apologize if I did, I am not using forums a lot and just wanted to point out that "I did plug it in". (and it was purchased 6 month ago..)

I tried to be very specific with my question that is:

Is there anything SPECIFIC on the 9871 in HYBRID mode?

And just thought anyone has a quick answer,  even if it is NO, IT IS NOT.

However, I found my work around which is to place a dedicated temperature sensor instead of using the chassis sensor (for which I used FPGA), so I can fall back to my working scan-mode configuration. The behaviour is funny though and I will narrow it down some day when I am bored.

Thank you for your reply, and nice greetings, Guenter

P.S.: Please do not waste your time with this problem any more, I consider it solved, unless you experienced similar situation.

[Bob_Schor]

Since you haven't been using the Forum a lot, you may not know that when you consider a problem "solved", you should click on the Post (or Posts) that "solve" it and mark it as a solution.  This benefits the Community in several ways:

• People who have a similar question can find this post and check out the "solution".
• People who look at current posts to see if they can help someone are "clued in" that "this problem is solved, don't waste your time".

Marking Solutions is a polite way of "giving back" to the Community.

Bob Schor

[nathan-p2]

I ran into this issue as well, and I wanted to document here what I did to resolve.  In my setup, I have a NI 9871 and have the cRIO configured in Hybrid mode as well.  Doing a TON on the FPGA, and just needed more RS485 ports for motor communications.  I have an RT main VI that runs, that downloads and runs the FPGA, and then it attempts to open the serial port on the NI 9871, but it would give error -1073807343.  

After trying a bunch of things, we found that adding a 5 sec. delay from when we download the bitfile and run the FPGA and the Open VISA.vi, resolved this issue for us.  We think the delay is needed because the VISA resources are not available until the Scan Engine is running, and it seems that there is some time needed after the scan engine starts for the VISA driver to have all the data it needs to operate correctly.  I would imagine this delay is caused by the startup of these resources.

I hope this helps someone who runs into this issue.  Until next time.

-Nathan P.