About FPGA VI

[Betty Boop]

Hello!

This is about running the FPGA VI.

I would just like to ask what is the probable cause of the FPGA VI outputting different answers everytime i run it (given that I'm not closing the VI or changing anything in the FPGA VI, I just "re-run" it).

Thank you! 

[RavensFan]

Uninitialized shift register?

Anything we say is just a guess since you didn't post a VI for us to look into.

[Betty Boop]

Hello.

The goal of the codes is to find the phase difference of two signals based on the I and Q data contained in the csv files. On the first run of the Host VI, I get the correct phase difference. The problem is, on the succeeding "runs" of the Host VI, I get different/incorrect phase difference which is indicated in the FPGA VI (and passed to the Host VI through the FIFO).

Attached are the zip file containing the Host and FPGA VIs, and the two csv files for the two signals.

The expected phase difference is 0.38.... rad.

Thank you.

[Betty Boop · Accepted solution]

Hello!

I already solved the problem. I used a separate VI for the reset (invoke method).

Thank you.

[RavensFan]

I was correct.  Your FPGA actually had uninitialized feedback nodes within your For Loops.  Try wiring an initial value into the initializer terminal of the feedback nodes.