Hello,
Is there any way to insert a pre-tcl script in labview so that whenever I compile my FPGA, it runs the tcl script?
I know I can create a build specification by project export for vivado and then inserting it in there, but I want to make this the default and not have to compile twice/export. I want to just click the run button and have it by default run the pre-synthesis tcl hook.
Everything seems pretty locked down under the labview compile hood, but I'm hoping theres at least some flexibility.
