Automatic insertion of IO Socket into FPGA target LV 2022

[Intaris]

I'm having some trouble with managing my CLIPs and IO Sockets for a project on a PXIe-6593.

We have a CLIP which we use for our project. HOWEVER, we have noticed that if we add this CLIP to the project (as per the recommendations in the LV help ( https://www.ni.com/docs/en-US/bundle/develop-flexrio-high-speed-serial-protocols/page/onfigure-labview-fpga-target.html : Yes, it's technically a different target, the missing documentation for the 6593 is a different topic) then upon loading the project after closing LabVIEW, we cannot compile, we get an encrypted envelope error, no idea which line of code, no help as to how to fix it.

We have adapted a cumbersome workflow where we maintain a project WITHOUT the CLIP, add it each time we need to compile, compile and then do NOT save the project. It's a pain, but we can compile.

However, now I have observed something even weirder. When I open a project on a network drive, it opens with no IO Socket. If I copy the SAME project to my local drive (both within the exact same folder structure) it finds and loads our IO-Socket automatically. Bear in mind, the CLIP is NOT added to the project via "Properties -> Component Level IP". The list of CLIPs there is empty.

When I open this file and it automatically adds the IO Socket, the code compiles. If I add it via "Properties -> Component Level IP" it will compile, but after saving will no longer compile. Clearly something weird (and wrong) is going on here.

Anyone got any ideas? Anyone experience anything similar? Am I finally gone mad?