Building a 6th-order Butterworth filter

[Proengin]

Hello,

For my FPGA project I need several implementations of Butterworth filters. Some of them are already available from the FPGA Math & Analysis palette : 2nd and 4th-order filters, but I also need a 6th-order filter.

First of all, I'd like to know if there is already something similar I could copy or adapt to my needs out there.

Second of all, assuming there isn't, I'm looking for advice from readers more experienced than I am about the best approach to take :

  . Knowing that my filter will be applied on 3 channels simultaneously, should I make a 3-channels, 6th-order filter directly, or just a one-channel filter? I don't have enough experience in FPGA to understand the tradeoffs.

  . I plan to start from the expanded code of an already implemented filter. Is there a prefered choice for the implementation? The 2nd-order and 4th-order filters seem to be the result of very different choices when I look at their expanded version.

Thank you for your time.

DLB

[Proengin]

Erratum: it's not the 2nd-order vs 4th-order expanded versions that are very different. It's the single-channel vs 3-channels, 2nd-order versions. It's like they were made by different people.

To see the expanded version of a filter, add it to a diagram, and fill the properties. Then right click and select the last line (convert to sub-vi). Open the new sub-vi diagram, right click the filter icon and select "open front view" (not sure about the real wording in English). This will show the diagram of what I call the expanded version of the filter.

DLB

[camerond]

Can't you just cascade a 2nd order filter VI and a 4th order filter VI, using the same frequency? That should give the right transfer function. But someone correct me if I'm wrong.

Cameron

[JLewis]

They were made by the same people, it's just that the multi-channel versions are solving a much more complicated resource-sharing problem. The logic that stores and retrieves the state for each channel is what makes it so different. If you have plenty of FPGA resources available, the simplest method is to just drop 3 instances of your filter--the point of the multi-channel implementation is to trade off speed for resources.

Cascaded 2nd order sections would be the way to go, but I'm not sure that simply cascading independent designs would get you exactly what you want. The order of the stages is another factor to consider when dealing with quantization--you want to go from most to least accurate to avoid compounding errors. You would need to find a 6th order cascaded design (using Digital Filter Design toolkit, the desktop floating-point design VIs, or a 3rd party tool), then scale/quantize the coefficients for use in the FPGA implementation. It's a tricky process.

Jim

[Proengin]

Thanks for the complementary information. My best option seems to be: get back to the algorithm designer for advice.

DLB

[AshwiniWini]

Hi,

I am also trying to something similar to what you had been trying. I want to implement Butterworth filter of 8th order on FPGA.

Wondering if you got solution to your issue, how did you end up implementing 6th order filter on FPGA.

Thanks and Regards,

Ashwini A Pandit