Basically, I am running into SCTL errors, so I am trying to offload as much of the processing as possible to the host. I have an idea that I can move a case structure that controls some less critical timing to the host and simply have the FPGA module act as a conduit (i.e. use the same DIO ports as some of the more critical time functions implemented on the FPGA target)... These less critical timing functions need to be accurate to 9 milliseconds or better (i.e. I change a logic level and hold that state for 9 milliseconds). Is this something I can do on the host?? Please let me know... Thanks!
