Can we have two different FPGA refernce running in the same VI

[cancancanopen]

Hello,

I had developed a FPGA VI which had code for analog input and analog output and digital output in a single while loop, and in another while loop a small CAN program, reference of this FPGA VI is called in RT VI for sending the commands and recieving the data.

I am facing a problem here, All the modules except CAN is working,No data is being received from the CAN when i do loopback {CAN0 and CAN1}

I have NI-9853 C series module plugged into my COmpact RIO.

Few questions,

1. CAN we have both CAN module and analog & digital modules in the same VI?

2.Suppose IF i create 2 FPGA VI's , can I call both FPGA VI in the same RT VI?

3. Can we have 2 different RT VI's in the same project?

4.How to build an application when RT VI and FPGA VI's are involved?

Thanks in advance

Rohith M P

[The_Devil]

Hello,

I will also answer your queries in the same numbered form:

1. I dont see any problem in using the CAN and the Analog and Digital modules being used in the same VI. What are you trying to do? If you can elaborate then I can say if you might face an issue with the same or not. But I dont think it will create any problem.

2. If you have 2 FPGA vi's you can use it for the same RT VI. Please refer to http://forums.ni.com/ni/board/message?board.id=170&message.id=221471&requireLogin=False

3. Are the 2 RT vi's on the same host? Are they calling the same subvi's?

4. I guess this tutorial will help you in creating application using the CRIO. http://zone.ni.com/devzone/cda/tut/p/id/3111

Regards,

Priyank

[cancancanopen]

Hi Priyank,

1.Analog and digital program- writing data and reading back the data from the respective channels.

   CAN module is again loopback between CAN0 and CAN1.Send data and recieve data.

   As of now I have two projects, one performing only analog and digital functionality and other project CAN functionality.

   When I run these seperately, my program works very fine,

   But when i combined my CAN module to the project which had analog & digital functionality, CAN module is not functioning properly, I am unable to    recieve any messages.

In FPGA VI i have added a seperate while loop for CAN, data sending and recieving.

2. I have two FPGA VI's one for analog module and one for CAN module, I am calling both the FPGA VI's in same RT VI. I got FPGA busy error.

3. 2 RT VI's call 2 different FPGA VI's is this possible ? I tried I got same FPGA busy error.

4.Creating application i meant creating a "exe". I have 3 different VI's , FPGA VI+RT VI+HostVI.

Host VI--->RT VI communication via shared variables

In RT VI i am calling FPGA VI refernce for communication.

Now is there any different way of creating exe?

Thanks & Regards

Rohith M P

[Bill_in_Detroit]

Rohith:

Please forgive me for jumping into this conversation, I was looking for some insight into my own issues with FPGA and CAN and saw your discussion.

You say you have the CAN working in a separate loop before you combine the two projects.  Can you perform the loopback test while in that separate loop?  If you cannot perform the loopback test, it may be that you have not supplied external power to the CAN1 port on the 9853 C-series module you are using.   I had this problem several years ago and it is an easy problem to overlook.

Have you seen the reference document 4YFEPK3Q ?

Sincerely, 

Bill 

[Robbob]

Rohith,

Only ONE FPGA bitfile can be running at a time.  This bitfile is created from a top-level FPGA VI that may be calling subvi's, but if you have one FPGA VI that works your CAN modules and one FPGA VI that runs your Analog modules, then you will not be able to run them in parallel, since the bitfile is generated to populate the entire FPGA.

You can close one reference to a bitfile and then load another bitfile programmatically, but it is almost always easier just to make one bitfile that encompasses all of your modules.

I hope this cleared that point up, since there seems to be some misinformation out there.

[CMal]

Rohith,

To address your second point, it is only possible to have one top-level FPGA VI on a given FPGA target.   This is why you are seeing a busy error.  The solution would be to create two subVIs, one for the analog module and one for the CAN module.  You may want to read the FPGA documentation in the LabVIEW help for more detailed information on this (from the LabVIEW help:  Contents >> FPGA Module >> LabVIEW FPGA Module Overview >> Developing FPGA Applications).

Chris M 

[cancancanopen]

Hello,

Thanks for the replies.....

@ Bill : We are giving supply to CAN1 port before running the VI. Loopback in seperate project is working fine.

@ Rob and Chris, - thanks for sharing the knowledge on the bitfile part,

Point No 2, 3 is closed.

But Point 1, I have a bit file which has both CAN and Analog&Digital modules. When I call in RT VI my analog and digital module is working and not CAN module.

I will see  here by changing the references programatically as per suggestion by Rob.

Can you pls share FPGA VI having both CAN and I/O module.

Regards

Rohith M P

[Bill_in_Detroit · Accepted solution]

Rohith:

If your CAN code works in loopback prior to the addition of the analog and digital code, and your analog and digital loop still works once you combine the two sections of code, then you probably need to look at how you are implementing the combined code.  I assume you have at least two parallel while loops (one for the analog / digital routines and one for the CAN routines) that will execute concurrently (perhaps at different rates) after some initialization routines have been run.  A good example showing parallel loops executing CAN on FPGA is located at  http://zone.ni.com/devzone/cda/epd/p/id/6162.

My theory is that the analog & digital loop is executing but the CAN loops are not.  If you add some code to the CAN loop portions of your FPGA code to give you some feedback that the code is executing (blink an LED) you could confirm or disprove that theory.  Alternatively you could look at the CAN output with another CAN device to confirm that your CAN send loop is executing.  If there is output but no input, check that the CAN code is implemented such that it is not running into transmit blocking or receive buffer issues.

Again, I apologize for stating what should be obvious, but I am providing the NI CAN FPGA example I did because it is much better than what was available from NI when I first started writing CAN FPGA code a few years ago (they were spartan at best back then).  Since you haven't posted any of your code I'm just making an educated guess here, and my guess is that at least one of your CAN loops is not initializing or running on either the send or receive side for one of the CAN ports (in the newly parallel FPGA code) and you are having CAN buffer overflow or blocking issues.  

Good luck.  I hope to hear you found the problem soon.

Bill