Can we implement lv random generator in hardware???

[mangood]

Hi ni

I have been use the lv random in my project and now I want to implement my project in hardware

can I implement this  LV random generator in hardware ???

If not then why ?????

Please I need some detail if you can

best regards

m.s

[nathand · Accepted solution]

The random number function is not available on FPGA. Good random number generation algorithms are complex. I would guess that the LabVIEW function calls one or more functions in the operating system that aren't available on FPGA. Also the random number output is a floating point, which was not supported on FPGA until recently (and I don't know if it's fully supported now, I haven't tried yet).

[sth]

Yes.  There is a Random number generator for the FPGA.  It is a Galois generator (check out Galois life history for entertainment.  He died way too young and we lost a lot of mathematics!).

Check out the Community page

https://decibel.ni.com/content/docs/DOC-1143

I have used this successfully.

[mangood]

thank you kuds for you

but i read this  ."" The algorithm is based on the use of multiple multiplicative congruential generators.""" about this generator

http://digital.ni.com/public.nsf/websearch/9D0878A2A596A3DE86256C29007A6B4A?OpenDocument

what the mean by  "" multiplicative congruential generators!!!!!"""

did any one have a clear information>>>??? 

[mangood]

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[sth]

It depends if you really care about the internals of the random number generator.  There is a whole field studying pseudo random number generation.   Note these are not truly random since they are generated by an algorithm.  The algorithm typically used is add the last integer to a large integer and then multiply by another large integer given overflows and dropping the high bits you get a fairly random number.  Chosing the two large integers is a bit tricky to make sure that the numbers won't loop.  You want it to cycle through all 2^N combinations.  There are refinements that involve the last N random numbers instead of just the last.

The Galois generator is a shift and xor operation IIRC and is easier to implement in a FPGA.  If you are really really interested you can read the original articles on the pseudo random number generators since they are documented.

Note that in the FPGA you get a value from 0 to 65535 and not a floating point number from 0 to 1.0.

[mangood]

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@sth wrote:

It depends if you really care about the internals of the random number generator.  There is a whole field studying pseudo random number generation.   Note these are not truly random since they are generated by an algorithm.  The algorithm typically used is add the last integer to a large integer and then multiply by another large integer given overflows and dropping the high bits you get a fairly random number.  Chosing the two large integers is a bit tricky to make sure that the numbers won't loop

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is you answer is explain to these words """congruential generators!!!!!""

[sth]

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@mangood wrote:

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is you answer is explain to these words """congruential generators!!!!!""

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Ah, so it is the word "congruential" that is bothering you.  This is because like all pseudo-random-number-generators (PRNG) they have defects.  There are better ones and the low order bits of this one have a serial correlation.  In fact there is some theorem that if you take the random numbers as coordinates in space, the points will lie on a hyperplane of that space.

Look up "conguential multiplicative pseudo-random number generators" and you will find some links on wikipedia and probably wolfram.  This is why they are not good for cryptographic applications.  I believe that Mersenne twisters are the best for statistically good generators.

To get back to the original problem, the Galois PRNG is not cryptographically good since there is a definite pattern in the bits.  Different than multiplicative generators but it is there.  But it is a fine generator for dithering or signal processing.