Cannot run Simulink dll at the same time as running real-time target VI

[gowen]

Hello

What I am trying to do is run a model dll created in Simulink to control some servo's through a CompactRio 9014. 

At the moment I have managed to create three VIs

1) In the FPGA target that performs the PWM on a desired channel

2) That takes the value of a network variable which contains the position required and feeds that to the 1st VI

3) A VI that runs on the host computer that modifies the value of the network variable to change the position

I can get these three VIs working and the servo controlled, but when I try to update the value of the network variable using the simulation, by deploying the simulation to the RT target and running it, it says

'Access denied: This target is already in use by another project or host computer.'

I assume as this is because the project is already connected to the cRio, so I disconnect and am able to deploy the model files. 

However when I try to run one of the VIs in the RT Targer along with the simulation I get the error:

'This VI is downloaded on the target but is not present in the project you are attempting to deploy.  All VIs on the target will be closed unless you choose to add the missing VI to the project.'

With a large number of missing VIs...

Would I be doing this wrong, i.e. is there a much simplier way to control the FPGA inputs using the simulation, or is there something I could have missed?

Thanks

Geoff

[Ricardo_SR]

Hi Geoff,

The reason why you are getting that message is because you are trying to download two different "applications" and LabVIEW RT can only run one application at a time.  When you build a VI from a LabVIEW project and you deploy it to the RT system, that VI  and its subVIs are ONE application.  If you have another VI for your simulation but it isn't part of your other VI(the one that feeds the position to the FPGA VI) then that is considered a different application.  When you try deploying this simulation VI by itself LabVIEW thinks that you want to stop the VI that is already running in the RT system and replace it with the new one.  

Since LabVIEW can only run one application at a time, that means that you have to embed the two VIs that you want to run inside a Main RT VI.

If I understood correctly you already have the following three VIs:

1) The FPGA VI  that generates the PWM.  This is the VI that talks to the IO modules and that runs in the FPGA backplane of the cRIO

2) The RT VI that reads the network variable and feeds the value to the FPGA VI

3) The Host VI that modifies the network variable.

If this is true, then what you need to do is open your 2nd VI (the RT one) and add to that VI your simulation VI as a subVI.  That way when you download or deploy the main RT (your 2nd VI) it will also download the simulation as part of that UNIQUE application.

I have some questions for you:

1) What version of LabVIEW are you using?

2)Are you using the Simulation Interface Toolkit ?

Since the 9014 cRIO is a VxWorks target I assume that you converted your Simulink model into an .OUT file instead of a DLL.  Have you done this?

National Instruments has a toolkit called Simulation Interface Toolkit that helps you create the RT and the Host VIs from a model DLL or model .OUT files and map the inports and outports of your model to hardware IO.

Here is a link to the SIT webpage in case you want to learn some more about it

LabVIEW Simulation Interface Toolkit (now the LabVIEW Model Interface Toolkit)

 You can still do what you want without SIT, as long as you use ONE RT VI that contains both your Call Library function for the model DLL/OUT as well as your network variable code 

Hope this helps

Ricardo

National Instruments

[gowen]

Hi Ricardo

Thanks for the quick reply! in answer to your question I am using Labview 8.6 and Simulation Interface Toolkit version 5.0.

I have managed to generate the .out file, that was the first part of the fun with this project!

That does sound like it is the key to success! However, how would I go about integrating the RT vi with the host vi? Would it be as simple as dragging the host vi into it? Would it need to be connected or configured in anyway?

I'm really sorry, but I am pretty new to labview and unfortunately one of the first people in our department to use it with the cRio hardware.

Many thanks

Geoff 

[Ricardo_SR]

Hi Geoff,

It seems that you are on the right track except for some concepts that I want to review:

A CompactRIO or cRIO has 3 different components:

1)      Real-Time controller (in your case a 9014)

2)      FPGA backplane (this could be a 9102, or a 9103, 910x, etc)

3)      I/O modules (like a 9401, 9263, etc)

When you write an application for cRIO you usually have three different VIs:

1)      Host VI – This VI is used as a user interface and runs in Windows (under “My Computer” in the LabVIEW project) This VI is optional because you might want to run the cRIO headless.

2)      RT VI – This is the VI that runs in the cRIO controller (in your case the 9014).  This VI lives under the cRIO target in your LabVIEW project. 

3)      FPGA VI – This is the VI that runs in the cRIO backplane like a 9102.  This lives under the cRIO >> FPGA target in the LabVIEW project.

The ONE application that I was talking about in my last post is for the RT VI.  There can only be one RT VI that gets deployed.  If you want to run multiple VIs in the cRIO RT, then you need to run those VIs as subVIs of one top level VI.

LabVIEW Simulation Interface Toolkit (SIT) has a tool called the SIT Connection Manager that creates two of these three VIs for you (the RT and the Host VIs).

Please refer to the following link about the SIT Help.  Go to the How To section.  It is organized in a kind of step by step tutorial.

https://www.ni.com/docs/en-US/bundle/371504f/page/download.html

In your case it is going to be a bit more difficult because of two things: One, you are using a VxWorks target.  Two, you want to use your own FPGA VI.

Let’s address each one of them:

1)      VxWorks target- To use the SIT Connection Manager you need to use a DLL not an OUT file, even though you need the OUT file for the cRIO VxWorks target.  The reason is that this tool needs to read the compiled model to know what the parameters, signals, inports and outports of your model are.  Because the tool runs in Windows you cannot open an OUT file (meant for a different OS) so you need to give it a DLL.  For this reason you will need to compile your model file into an OUT file and a DLL.  Once you give a DLL to the Connection Manager and you select your cRIO as the execution target, keep doing the rest of the steps as the help says.  LabVIEW will identify that you are using a VxWorks target and will download the OUT file to the cRIO.

2)      Custom FPGA VI – LabVIEW SIT has some FPGA bitfiles (compiled FPGA VIs) that it can use.  When you open the SIT connection manager and go to the Hardware IO mapping section it asks you to select the bitfile.  If you want, you can select one of the shipping bitfiles but iIf you want to use your own, then you will need to do some changes to your FPGA VI , recompile it and save the bitfile in a specific location with a specific name.

What I would suggest is that you start with a very simple example and using one of the shipping bitfiles.  Look into the following path for a very simple Sine wave generation example:

C:\Program Files\National Instruments\LabVIEW 8.6\examples\Simulation Interface\Sine Wave

Because you are running a VxWorks target you will need to recompile this example model sinewave.mdl to an OUT file.

Hope this helps and let me know if you have more questions.

Ricardo

National Instruments

Systems Engineering

[gowen]

Hi Ricardo

Thank you again for the reply.

The model simulation is already running through the SIT, it was compilied as a DLL first, then after some fiddling I managed to get the .out file. I put the .out file in the folder with the dll as advised and then run the SIT connection manager to get the simulation on the cRio.

I have also created the custom FPGA bitfile for my device, however I do not want the simulation to drive this directly if possible. 

What I am trying to do is run the simulation from VxWorks, take the output angle from the simulation and then in the FPGA convert this into a PWM signal to drive a servo. I have already made the VI which does the PWM conversion.  

However as the SIT manager only lets you create a simulation within a Host VI, I am having difficulty with deploying it to the cRio at the same time as running the conversion FPGA file.

What I have got working is a host VI which uses a slider to set the angle of the servo, this in turn is sent to the RT VI via a network variable. This is then referenced to the FPGA VI to do the conversion and output the signal. This I can get working fine.

The issue arises when I want to take the reference from the Host VI which controls the simulation, in essence take the angle that is output and sent it to the RT VI using the same method. It will not let me run the two VIs at once as they are I assume in essence two RT VIs, just under different targets and it cannot deploy one whilst the other is running. 

I do not know if this is possible.. from the sounds of it, it doesnt appear to be... 

However I can only assume that if the simulation is deployed to the cRio, then there must be a VI somewhere, or value that could be used as a variable for the control... the problem is trying to establish where it is, or how to manipulate the code to do it...

Regards

Geoff

[Ricardo_SR]

Hi Geoff,
 
SIT Connection Manager doesn't create the simulation within a Host VI.  I think what you want to do is exactly what SIT does.
In the SIT Connection Manager there are three types execution targets, meaning that there are three different targets where the simulation can run:

1)  Simulation Environment - This is when you run your simulation in MATLAB Simulink and use LabVIEW as a user interface. In this case you don’t use a DLL /OUT you use a mdl file. This is not what you want to do.
 
2)  Real-Time Target - This is when you want to run your simulation in the real-time controller.  When you select this option SIT Connection Manager generates the two VIs I was talking about (the Host VI and the RT VI called Driver VI) plus a new LabVIEW project.  The driver VI has several blocks; one of them does the calls to the DLL /OUT file.  Since you choose Real-Time as execution target, when you run the Host VI, LabVIEW deploys silently the Driver VI along with the DLL/OUT file to the RT (cRIO).  This means that the simulation happens on the cRIO.  I believe this is what you want.
 
3)  Driver VI on Local Host - This option generates the Driver VI just like for the Real-Time target option but in this case you run the Driver VI in your computer. This is used when you want to make sure that the compiled version of the model DLL behaves the same as your mdl model.  Not what you want to do right now.
 
For what you want to do, choose the Real-Time target option.  This will create a new separate project in the same folder where you keep the DLL with the name <model name>Driver.lvproj.  This LabVIEW project will contain a cRIO target and under that target you will see the Driver VI.  This project and Driver VI are called and deployed silently to the RT controller by LabVIEW when you run the host VI and run the simulation.  Again, with this execution target the simulation occurs in the Real-Time box.  One thing to add is that SIT will “finish”(add extra code to your  Host VI) when you finish configuring SIT Connection Manager.  This extra code is the necessary code to communicate to the RT while the simulation occurs in the RT box.  This means that the data you see in the Host VI is actually coming from the RT via TCP/IP.
 
More questions:
What generates the angle of the servo? Is it the simulation? Or is this angle completely independent from your simulation?    If your simulation is the one generating the value for the angle, then in the SIT connection manager you map directly the Outport of your model to the FPGA output that you want.
 
This might be easier to understand with the sine wave generation example.  If you open the sinewave.mdl located at C:\Program Files\National Instruments\LabVIEW 8.6\examples\Simulation Interface\Sine Wave you will see that there is an inport that goes into a sum. The other input to that sum is a Sine Generator block.  The output of that sum goes into an outport. 

When you use SIT Connection Manager and select Real-Time target you will be able to select the model DLL and do the mappings.  On your left side in the SIT Connection Manager window the second option is “Mappings”.  Click on that option.  This will allow you to map the parameters and signals of your model to LabVIEW controls and indicators.  So, if you had a numeric control in your LabVIEW front panel (HostVI), you can use the SIT connection manager to map that control to your Sine Generator block parameters (Amplitude, Frequency, etc).  Once you do that, the last option under Categories in the SIT Connection Manager is Hardware I/O.  If you click there you will be able to map the inports and outports of your model to the physical I/O. In this case if you have an analog module you can map the channel 0 to the Inport of your model.  That way, whatever you read on that channel gets passed to the model.  You can also map an analog output channel to the Outport of your model.  So whatever the output of your model is it gets mapped to the actual hardware output.

All the code that is needed to map the IO to the inports and outports and to map your LabVIEW controls and indicators to your model parameters and signals are created by SIT.  You just have to click RUN.

Hope this clarifies a bit more what SIT does. Let me know if you have more questions
 
Ricardo
National Instruments
Systems Engineering

[gowen]

Hi Ricardo

I do understand that the simulation does not run in the Host VI and on the cRio, however to run the simulation, it needs to be set up on the Host in a VI. You cannot run the SIT toolbox from within a VI on the cRIO. Sorry if it has come as across as that what I thought...

The simulation is of a SimMechanics model of a robot, its joint movement in degrees is the output I want. I want labview to process this to PWM. I know that this can be mapped directly, but there are other measurements that I would like to take and process along with the simulation. I do know about the mappings, both VI and hardware... but this is not what I want to use.

Basically the concept of the project is to model a robot leg. The simulation moves the leg and the forces underneath the foot are caluclated (assessing the weight over the foot during movement). I have then built an exact model of the leg which I want the simulation to control. I would like labview to take these angle measurements of the servo positions from the models and output them to the leg that I have built. In essence, labview will convert the degrees to PWM signals and will measure the forces under the foot using force sensitive resistors. I then wish labview to calculate the difference between the model forces and the measured forces to see if they are accurate.

However the issue I am having is that I cannot seem to run two RT vi's at the same time.... As I will need one to take the sensor measurements, independantly of the simulation. The only thing I can think of is creating inputs into the model in simulink and mapping the hardware IO to those and getting the results this way.  Or is there a way of calling the seperate VI so that it can be deployed and used at the same time? 

Unless I modify the custom FPGA bitfile... but this isn't really what I want to do as I would like more control within the project.

I am not sure if this is making any sense... As this is what I have been trying to establish from the start, but I dont think I am making it clear... I am not wanting the outputs to go directly to the I/O, I am in essence trying to make a 'buffer' which reads/edits the information in the cRio.

I hope that's a bit clearer

Geoff

[Ricardo_SR · Accepted solution]

Hi Geoff,

I think I understand better what you are trying to do and what you have done so far.

If I am not mistaken you have gone through the SIT connection manager, configured your RT target (select DLL, mappings and hardware I/O) and this one has done its "magic".   If this is the case look for the LabVIEW Driver project that got created by the SIT connection manager.  This should live in the same folder where your DLL is.  Open the Driver project, look for the Driver VI and open it.  Then go into the subVI # 5a with the name Base Rate Loop.  This is the SubVI that reads/writes to hardware and reads/writes that data to the model DLL/OUT.  If you want to read the output of you model and then manipulate the data this is where you need to add your code.

Inside this Base Rate Loop VI there is a subVI with number 4 and called SIT Take Model Timestep.  This VI is the one that does the call to the model DLL.  The output of that VI is your data coming from the model.  This data goes into subVI # 5 which is in charge of writing that data to the hardware.  Since you want to manipulate this data coming from the model, you need to grab the data from the wire coming out of subVI 4 (SIT Take Model Timestep) before it gets to subVI # 5.

In this Base Rate Loop VI you will see that there are some empty frame structures.  These frames are for you to put whatever code you want.  The reason is that any changes you do to the driver VI and subVIs that are not inside these frame structure will get lost if you decide to go into the SIT Connection Manager again, and do some changes.  The driver VI gets re-scripted everytime you do something in the SIT Connection Manager.  Anything inside those frames won't be erased.

So, if you have some code that you want to run in parallel to the simulation you just have to drop it inside this driver VI.  Most likely inside this subVI 5 (Base Rate Loop). To add your code just drop the VI inside one of these frames and do any changes to it so that it can read from the model data.    By the way, the data from the model (subVI 5) is in an array.  To know the index of each element in the array and its meaning look for a file in the same folder where the DLL is with the name <model name>ports readme.txt.  This file has a descritpion of the inports and outports and their indexes.

This driver VI gets called when you run the Host VI so you won't have to run it sepearately. 

Regards,

Ricardo

National Instruments

Systems Engineering

[gowen]

Hi Ricardo

That is just what I am looking for I think! 🙂 I will give it a go tomorrow, but is sounds like it should work perfectly!

Thank you for all your help! Sorry I didn't explain myself well enough the few times!

Many thanks

Geoff 

[jarcTek]

I am trying to create an application for Hardware in the Loop testing of an automotive suspension system. I successfully measure and send data to the physical system by means of a VI and NI-DAQ components. I also am successfully employing a Simulink model as a DLL, and running the Simulation Interface Toolkit with Driver VI on LocalHost (I don't have access to a Real-Time computer and want to do the test from a Desktop running Win 7). The simulation runs fine when employing data that I input.

Now, I want to be able to combine these two VIs and have my simulation READ and WRITE data to the NI-DAQ components on Real-time.

I am not certain if the modifications needed should be added to the Base Rate Loop VI, of if I could just have separate VI's running in parallel and sharing variables. The Ports Readme file on my project is empty.

Thank you for your answer.