Communication problem between FPGA VI and Host-PC VI

[Jasper_B]

Dear,

I am trying to set up communication between an FPGA an the host-PC using FPGA FIFO's.

The communication still has some problems and I don't know what would cause them.

Labview gives me the following reason "The transfer did not complete within the timeout period or within the specified number of retries."

What is wrong with my labview program? How can i solve this?

The Project can be found in attachment.

Best regards,

Jasper Beurms

[crossrulz]

It doesn't look like you are writing your Shaft Speed inside of the FPGA.

Nevermind.  I didn't scroll down to find it.  But I am noticing that your writing to the Shaft Speed DMA is dependant on analog levels.  Are you sure that line is going through the transition threshold you need?

[Jasper_B]

I tried the program again but instead of using simulated I/O i used constants so that i am sure that values are written to the "Shaft speed" fifo. The same problem still occurs. The error occurs with all the FIFO's. It is not always the same one wich is causing the problem. 

[ThiCop]

Hello Jasper,

Are you fully familiar with how DMA FIFOs work on a cRIO?

Some general questions:

- Is there a specific reason that you need to use DMA FIFOs?

  You seem to only require a 10 msec acquisition rate?

- Wouldn't it be easier to just use the Scan Engine in the case you don't need to go below 10 msec?

The Scan Engine should allow you to do acquisitions at this rate without even having to implement FPGA code yourself.

Another benefit is that the Shared Variables created/published by the Scan Engine are also by default visible over the network/

If want to use DMA FIFOs, then I would suggest you take a look at the Compact RIO Developer's Guide: http://www.ni.com/compactriodevguide/

I would advise that you read out the DMA FIFOs on a VI that is running on the RT Controller (RT VI) and then send those values from the RT VI over the network to your Windows VI.

You could use for example Shared variables to sent values from the RT VI to the Windows Host VI.
Another solution might be to use network streams or more custom TCP/IP communication.

If these concepts are new to you, then please have look at the Compact RIO Developer's Guide: http://www.ni.com/compactriodevguide/

This Guide should explain you all the basics you need to know.

If something is unclear or requires further explanation, then please let me know.

[Jasper_B]

I have used DMA FIFO's before but only for communicating between the FPGA and the real time controller. I want to acquire the data and send it as quickly as possible. I thought that FIFO's where good for this. Shared variables are not recommended if there value changes a lot in a short period of time (correct me if IM wrong). The structure I am using now has worked between FPGA and real time controller but wont work between FPGA and host-PC. I don't know why.

[Todd_Lesher]

DMA is direct memory access. The FPGA is on a bus with the RT processor, but not with the PC. I've heard network streams are the way to go.

[Jasper_B]

Isn't it strange that labview allows you to read data from the FIFO on the host PC? It allows you to open a FPGA reference and invoke node. Why should this be possible if this isn't destined to work anyway?

[GerdW]

Hi Jasper,

LabVIEW allows it because there is hardware that supports such FIFOs.

Your hardware doesn't seem to…

[ThiCop · Accepted solution]

Hello Jasper,

Based on your feedback a good approach could be to use DMA FIFO from the FPGA to the RT Controller and to use network streams to send everything over the network.

Please note that (based on your original code) it might also be useful to take a look at how you can use DMA FIFOs with interleaving.

PS: I'm mentioning this because there is a limit on how many DMA FIFOs you can use onach RIOtarget.