08-29-2014 06:58 AM
I'm trying to compile a "user CLIP socket" for the NI PXI board - 7951R which has a Virtex-5 LX30 FPGA from Xilinx, but I got the bellow message from NI Compiler, this message is in error report Xilinx.log.
It says that module Puma15Top was not found.
But this module is a NI property and is automatically compiled by NI Compiler.
The compiler automatically generates these files (Puma15Top...) that are passed to the compiler of Xilinx. The Puma15Top files are in the path, i.e: C: \ NIFPGA \ compilation \ Told_F_I_CC5DC260 \ source_files.
This folder name is automatically generated by labview (Told_F_I_CC5DC260) for each different project or compilation.
So I have no way to configure in CLIP files where it'll be Puma15Top, once the path is automatically generated during compilation by Labview.
Does anyone have any idea how to solve this problem? Or have you experienced some like this?
Following error log:
### XstSynthesis ###
Puma15Top
Reading design: Puma15Top.prj
==================================================
* HDL Compilation *
==================================================
Compiling vhdl file "C:/NIFPGA/jobs/Cm9xA8x_LaF6U1d/CLUC001_Conf.vhd" in Library work.
Entity <CLUC001_Conf> compiled.
Entity <CLUC001_Conf> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/NIFPGA/jobs/Cm9xA8x_LaF6U1d/CLUC001_CLIP.vhd" in Library work.
Entity <CLUC001_CLIP> compiled.
Entity <CLUC001_CLIP> (Architecture <rtl>) compiled.
Entity <CLUC001_CLIP> (Architecture <behavioral>) compiled.
ERROR:Xst:2472 - Top module <Puma15Top> was not found.
ERROR:Xst:2469 - Please specify the correct library via the -work_lib switch.
-->
Total memory usage is 149596 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesis" failed
Thanks in advanced!
09-01-2014 01:26 PM
JEMP,
What version of LabVIEW and NI-RIO are you using?
Best,
Guilherme Klaus
Application Engineering
National Instruments Brazil
09-01-2014 02:19 PM
Hi Guilherme, thanks your answer.
LABview - 2010 SP1 (10.0.1) (32bits)
NI RIO - 3.6.0
Regards
09-02-2014 07:12 AM - edited 09-02-2014 07:13 AM
JEMP,
This problem was solved in later versions to NI RIO 12.0. According to this LINK you can download any version later than NI RIO12.0.
Any doubt let me know.
Best,
Guilherme Klaus
Application Engineering
National Instruments Brazil
09-02-2014 09:37 PM
Hi Guilherme,
Thanks your suggestion, I upgraded NI-RIO to 13.1.1 version but the problem persists, as shown below:
Project: T_old.lvproj
Target: F (RIO0, PXI-7951R)
Build Specification: I_2
Top level VI: I.vi
Compiling on local compile server
Compilation Tool: Xilinx 11.5
Start Time: 2/9/2014 18:03:51
Run when loaded to Fpga: FALSE
JobId: z8Cq8B4
Working Directory: C:\NIFPGA\compilation\Told_F_I2_F3177096
Compilation failed due to a Xilinx error.
Details:
ERROR:Xst:2472 - Top module <Puma15Top> was not found.
ERROR:Xst:2469 - Please specify the correct library via the -work_lib switch.
-->
Total memory usage is 149596 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesis" failed
Start Time: 18:03:51
End Time: 18:05:19
Total Time: 00:01:27,414
Best,
JEMP
09-03-2014 11:31 AM
JEMP,
I need to post the zip file from NI MAX Technical Report
To create this report, you can follow the link: To generate a report on the local system.
Best,
Guilherme Klaus
Application Engineering
National Instruments Brazil
09-03-2014 12:54 PM
Guilherme,
Attached you have the report ni_support.zip.
Regards,
JEMP
09-05-2014 04:44 PM
Jemp,
Could you please attach a copy of the log file to this post? At what point in the compile process does this error occur?
Thanks,
Guilherme Klaus
Application Engineering
National Instruments Brazil
09-05-2014 04:57 PM
Jemp,
You trying to develop a socketed clip for a custom FAM?
Thks,
Guilherme Klaus
Application Engineering
National Instruments Brazil
09-08-2014 12:15 PM
Hello JEMP,
Coul you please provide the information requested by GKlaus?
We need this to work on this issue.
Thank you,