Compilation placement error while changing ports from port0 & port1 to port2 & port3 on NI PXIe-6592R

[Anitha.G]

Hi,

Board used      : NI PXIe-6592R (Kintex FPGA)

Ports available : 4

We have enabled and tested ports 0 & 1 . Now to test other two ports 2 & 3, I  just changed the port selection from port 0&1 to port 2&3 and changed the ref clk slection (from MGT_refclk0 which is for Q3 transceiver port 0 &1) to MGT_refclk1 in same design on NI Labview. Corresponding ports are also changed in RTL top file but facing below placement issue . Please suggest any changes to be done.