08-06-2024 05:30 PM
I need to convert a single precision float value to a four byte U8 array in the FPGA to transmit using UART code that I've already generated also running on the FPGA. There are reasons why I need to perform this operation in the FPGA and not on the host side, which I will not go into here. I'm struggling to find solutions that don't include using string functionality, which obviously is not available to me on the FPGA side. Thanks very much in advance for any suggestions.
Solved! Go to Solution.
08-06-2024 03:32 PM
Hi Sean,
I'm trying to do something similar to your solution, but without converting to ASCII. I will have a single float value ranging from -0.5 to +0.5. I would like to maintain 4 digits for the decimal/fraction, so 0.XXXX. I want to convert it to an array of four U8s (or it could be eight U8s). Can you help with what mods I would make to your VI to accomplish this?
Thanks much.
JJ
08-06-2024 05:50 PM
Hi johnsoja,
Check this:
Regards,
Raphaël.
08-07-2024 08:54 AM
Hi Raphael,
Thank you very much for the prompt response and that approach does look like what I need. However, when I attempted to open the .vi, I get the error "Support file regeneration required". I attempted to perform the regeneration, but that fails. See error screenshots below. Can you advise on how to correct these issues?
Thanks again.
JJ
08-07-2024 11:39 AM - edited 08-07-2024 11:41 AM
Edit: Oops solution is already there. My bad. Ignore what I added.
Hi John,
If you are okay with eight U8s and some precision loss, I tried something that might work for you.
Hope this gives you some ideas.
08-07-2024 11:42 AM
This issue is closed based on Raphael's solution located at : https://forums.ni.com/t5/LabVIEW/Flatten-floating-point-on-FPGA-for-multichannel-DMA/m-p/2576179#M77....
I had trouble regenerating the IP Integration node on my PXI chassis due to the often mentioned incompatibility between Windows 10 and ISE 14.7 and Vivado. I was able to perform the regeneration on another Windows 7 machine and all is working.
Thanks again to Raphael for the help!
08-08-2024 09:00 AM
Please kudo this idea to add support for bit reinterpretation (type cast) in FPGA.
08-08-2024 09:20 AM
Done