DMA FIFO on myRio FPGA can't compilate

[Spurbruenette]

Hi,

i wanna record a video from a Webcam that I have connected via USB to my myRio1900. As far as I know the record itself isn't possible on the myRio so I wanna stream it via the FPGA onto my PC. The FIFO's are configured as DMA and I have configured the compilation for a local Server.  The Problem I have is that I can't compilate the FPGA vi for a reason I don't know (still pretty new to Labview). 

[Intaris]

What is the error message you receive?

[Spurbruenette]

Hi,

this is the error message (don't really knows what it means)

[Intaris]

Have you installed the FPGA compile toolkit? Vivado?

[Spurbruenette]

Yes, I have installed this

[ZYOng]

What is your LabVIEW FPGA and ISE Compilation Tool version? What is your OS version?

Can you try to compile a FPGA VI without any FIFO?

Error -123002 or -123011 When Compiling LabVIEW FPGA Code Locally

[Bob_Schor]

Those "pictures" are intriguing.  When I made an FPGA DMA channel for my myRIO (using LabVIEW 2019, with the 2019 myRIO Software Toolkit), there were no Invoke nodes that resemble yours that I could find.  I also never imagined doing a direct DMA from the FPGA FIFO (inside the myRIO) directly to the PC (connected to the myRIO using TCP/IP).  

What I do (in the "Target", or the myRIO part of the LabVIEW RT Project) is to have the Timed Loop initiate a sample, DMA the data from the FPGA FIFO to a 2D Array in the Timed Loop, and stuff this away in a DVR, which (of course) lives on the myRIO.  Between bouts of data acquisition, a parallel process running on the myRIO transfers the data from the DVR to the Host (PC) using Network Streams (over TCP/IP).

In order to understand what (and how) you are handling your data transfer from the myRIO FIFO to the PC, I'd really want to look at "sample code" that includes:

• Demo code for establishing communication between PC and myRIO, including getting the PC to establish communication with the myRIO.
• Demo code for the RT Target that establishes communication with the PC and starts the FPGA.
• A simple FPGA routine that generates "known" data (for example, an array of 1's, then an array of 2's, etc.) and DMA's them to the RT Target.  Include the FPGA code that does whatever you are trying to do to get the data directly to the PC.
• Make sure we see the code that includes the FPGA DMA calls you reference.

You'll need to make a Demo Project file, of course.  Please also provide the following critical information:

1. Version of LabVIEW you are running, including Year and Bit-ness (32 or 64).
2. Version of the myRIO Software Toolkit.
3. Version of the Firmware on the myRIO.
4. From MAX, a listing of the Hardware, preferably with the right-hand pane showing the details of the myRIO.
5. From MAX, a listing of the Software, especially for the myRIO Target.

I'm currently working with LabVIEW 2019 and myRIO Software Toolkit 2019.  I have also successfully installed LabVIEW 2021 and myRIO Software Toolkit 2021, but have not yet "switched" to using it as the rest of the Team is using 2019.

Bob Schor

[Spurbruenette]

I'm using the LabVIEW myRio Software Bundle 2019 32bit (LabVIEW 2019 and myRio Toolkid 2019). 

The Demo Code is attached below.

Thanks for your help!

[Bob_Schor · Accepted solution]

Now I understand your problem -- the nomenclature is a little bit confusing.

Consider the LabVIEW Real-Time situation -- you have a PC (the Host) connected to a Real-Time Target (the myRIO).  You do all of the LabVIEW development on the PC (Host), but design it to run on (and be deployed to) the myRIO (Target).

So now go to the myRIO.  It has a processor that can execute LabVIEW code, the VIs that the Host sends to it.  It also has an FPGA that the PC cannot "see" directly.  The PC develops the (LabVIEW) code for the FPGA, but in the Project, the code is shown as part of the myRIO Target. 

     And this is the source of the confusion.  The DMA is a communication path between the FPGA (the Target) and its Host, which is the myRIO!  The myRIO can DMA data to a buffer on its FPGA (this would be a Host-to-Target DMA), or the FPGA could DMA data to its Host, the myRIO.

     To get the data, collected in FPGA memory and transferred "as fast as possible through secret back channels" to its Host, the myRIO, all the way to the PC, requires two separate steps:  DMA Transfer from Target (FPGA) to Host (myRIO), where it is stored somewhere, and a second transfer (I use Network Streams for this step) from the LabVIEW RT Target (myRIO) to the LabVIEW Host (PC).

     The PC has no direct pathway to the FPGA that lives in its RT Target.  It is easy to overlook this step, particularly if trying to learn FPGA programming by yourself, especially since the PC seems so intimately involved with developing the FPGA code and bitfiles.  Hope this clarifies the situation.

Bob Schor

[ZYOng]

Understanding Communication Options Between the Windows HMI, RT Processor, and FPGA  summarizes this very well.